Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-07-09
2001-09-11
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S213000, C348S537000
Reexamination Certificate
active
06288699
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an image display device including a sampling section for sampling a video signal and a sampling signal generating section for indicating a sampling timing to the sampling section, and more particularly relates to an image display device capable of displaying a high quality image even when the characteristics of an active element of the sampling signal generating section vary according to each sampling signal generating section, without causing a lowing of the image quality due to a difference in the timing.
BACKGROUND OF THE INVENTION
For example, image display devices such as an active matrix type (active matrix drive type) liquid crystal display device in which pixels are arranged in a matrix pattern have been widely used. As illustrated in
FIG. 23
, n lines of data signal lines SL
1
to SL
n
and m lines of scanning signal lines GL
1
to GL
m
that intersect the data signal lines SL
1
to SL
n
are provided in a pixel array
102
of an image display device
101
, and a data signal line driving circuit
103
outputs video data D to the data signal lines SL, while a scanning signal line driving circuit
104
selects each of the scanning signal line GL sequentially. Therefore, the video data D is written in a pixel PIX corresponding to a combination of a scanning signal line GL and a data signal line SL, and a display state of each pixel PIX is determined. Incidentally, when there is a need to specify a position, for example, the first scanning signal line GL
1
, a subscript numeral representing the position is referred to. On the other hand, when a general term for the lines is referred to or when there is no need to specify a position, a subscript numeral is omitted like the scanning signal line GL.
Here, in the image display device
101
, the video data D are supplied as a video signal DAT to each pixel PIX by a time-division system, and the data signal line driving circuit
103
samples the video signal DAT in synchronization with timing signal such as a start signal SPS and a clock signal CKS, amplifies, if necessary, and outputs the video data D to the respective data signal lines.
More specifically, for instance, as shown in
FIG. 24
or
25
, when the start signal SPS is input to a sampling signal generating section
132
of the data signal line driving circuit
103
, a shift register section
133
shifts the start signal SPS in synchronization with the clock signal CKS. Moreover, a buffer section
134
generates sampling signals S
1
to S
n
representing sampling timings corresponding to the data signal lines SL
1
to SL
1
, respectively, according to outputs N
1
to N
n
of the respective stages of the shift register section
133
.
On the other hand, in a sampling section
131
of the data signal line driving circuit
103
, a sampling circuit AS provided for each data signal line SL determines as to whether the video signal DAT is to be output to the data signal line SL, according to corresponding sampling signal S (/S). As a result, video data D are output to the corresponding data signal lines SL.
Here, as shown in
FIG. 26
, since a finite signal delay is introduced in the data signal line driving circuit
103
, each sampling signal S changes after a delay time td from the clock signal CKS. The delay time td is determined according to the characteristics (mobility, threshold voltage, etc.) and size of a transistor constituting the data signal line driving circuit
103
. Thus, the clock signal CKS is applied at such a timing that produces a phase difference ta between the video signal DAT and clock signal CKS by taking the delay time td into consideration, and a sampling time point t
101
(time point of the terminating end of pulse: in this case, the time point of the decay of the sampling signal S) is set so that it is a time point in a supply period of the video data D, and more preferably a time point in the vicinity of just before a switching time point t
102
of the video data D (td≦ta).
In the following description, for the sake of convenience of explanation, the phase difference ta between the video signal DAT and the clock signal CKS is defined as the difference between the switching time point t
102
of the video data D and the decay time point of a clock signal CKS used for generating a sampling signal S corresponding to the video data D. Besides, the explanation will be given by discussing the relationship between the sampling signal S
1
of the data signal line SL
1
and the corresponding video data D
1
as an example.
In this case, the sampling circuit AS
1
can sample the video signal DAT at correct timing, and the video data D
1
of a correct value is output to the data signal line SL
1
. Moreover, when writing the video data D
1
to the pixel PIX, it is necessary to hold video data D
1
for a predetermined time. Since there is a sufficiently long time before a sampling time point t
101
after the video data D
1
is stabilized, the pixel PIX can have a sufficient hold time. As a result, the image display device
101
can display a high quality image without ghosts or blurs.
With the above-mentioned structure, however, for example, if the delay time td is changed due to a variation of the production process, the data signal line driving circuit
103
can not sample the correct video data D, causing a problem that the image quality is lowered by ghosts, blurs of the image, etc.
More specifically, when an actual delay time tdx is longer than the imaginary delay time td due to a change in the delay time td, as illustrated in
FIG. 27
, there is a possibility that a sampling time point t
101
x indicated by the sampling signal S
1
comes behind the switching time point t
102
of the video data D
1
(tdx>tax) . In this case, since the data signal line SL
1
is supplied with data different from the intended video data D
1
because an inaccurate signal is output during switching from the video data D
1
to D
2
, or the next data D
2
is mixed in the data signal line SL
1
. As a result, blurs of the image and ghosts occur.
On the other hand, as illustrated in
FIG. 28
, when the actual delay time tdy is shorter than the imaginary delay time td, the time between the time point t
100
at which the video data D
1
is stabilized and a sampling time point t
101
y indicated by the sampling signal S
1
becomes shorter, and thus there is a possibility that the above-mentioned hold time is not ensured (tdy<tay). In this case, it is impossible to write the video data D
1
of a correct value to the pixel PIX, causing blurs of the image.
The above explanation is given with reference to an example in which each sampled video data D is directly written to the pixel PIX like a point sequential driving method. However, the same problems also occur when a line sequential driving method is employed. Specifically, in the line sequential driving method, once each video data D is held by a sampling and hold circuit, the video data D is applied to each pixel PIX, and the sampling and hold circuit also requires a hold time. Thus, in either case, there is a difference in the timings of the sampling signal S and the video signal DAT, and if the phase difference is out of an appropriate range, blurs of the image or ghosts occur, preventing display of a high quality image.
Therefore, especially in resent years, there are demands for a small-sized, high-resolution image display device and a reduction in the packaging cost. In order to meet such demands, a technique of forming driving circuit such as a data signal line driving circuit and a pixel array integrally on a single substrate has been noted. In such an integrated driving circuit type image display device, in order to increase the display area, a polycrystalline silicon thin film transistor formed on a quarts substrate or glass substrate is often used as an active element. In particular, in the case of a transmissive type liquid crystal display device which has been widely used at present, the substrate is made of the above-mentioned material because the substrate
Kubota Yasushi
Kuwabara Nobuhiro
Sakai Tamotsu
Shiraki Ichiro
Yoneda Hiroshi
Bell Paul A.
Conlin David G.
Dike Bronstein Roberts & Cushman
Saras Steven
Sharp Kabushiki Kaisha
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