Image display device

Communications: electrical – Land vehicle alarms or indicators – Internal alarm or indicator responsive to a condition of the...

Patent

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Details

340721, G09G 102

Patent

active

050289179

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

This new invention is basically an improved image display device that displays gradient images, and more specifically, is an image display device that displays data in multiple areas on a display screen with discretely different ranges of gradation by matching the required range of image data gradation to the range of gradation for the display unit.


BACKGROUND ART

For an image display device that displays gradient images, the required range of gradation is usually selected from the range of gradation for the image data, and is displayed after being matched to a fixed range of gradation for the display unit. For example, an image display unit used for computer tomography can accommodate image data having gradation ranges from -1000 to +3000. A gradation range (called a window and level) that displays the states of individual sections most appropriately is selected according to the desired sections, and is displayed within the windows and levels of fixed gradation for the display unit. A gradation conversion circuit is built into the display device to match the selected range of image data gradation to that of the display device. Such image display devices as described above have conventionally required multiple gradation conversion circuits, which is not desirable due to increased hardware requirements when an operator wishes to display multiple sections on the same screen with each section displayed in a discrete range of gradation.


DISCLOSURE OF THE INVENTION

This new invention provides a display device that displays data in multiple areas of the same screen in discrete ranges of gradation while minimizing increased hardware requirements.
The image display device of this invention consecutively reads one frame of image data written to a first frame buffer (20) in during the display cycle of the display unit (80). The said display device writes image data each time to a write-enable area of a second frame buffer (50) as specified by a write control circuit (40) after gradation conversion processing is executed using a gradation conversion circuit (30). The image data of the second frame buffer is converted into a video signal by a video signal-generating circuit (70), and is displayed by the display unit (80). By repeatedly setting new gradations and write-enable areas, image data having discrete gradations for individual areas is written to the second frame buffer.


BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 shows the conceptual diagram of the preferred application mode of this new invention.
FIGS 2 and 3 show the individual circuit diagrams of the frame buffers of the preferred application mode.
FIGS. 4 and 5 show the performance of the preferred application modes of this new invention.


BEST MODE FOR CARRYING OUT THE INVENTION

Application examples of this new invention are described in detail by referring to the following drawings. FIG. 1 shows a conceptual block diagram of the preferred application mode of this new invention.
In FIG. 1, the number 20 indicates the first frame buffer. Control circuit 25 of buffer 20, gradation conversion circuit 30, write control circuit 40, and keyboard 90 are connected to bus 11 of CPU 10, which generates image data to be displayed. Data and control signals are exchanged between these circuits and CPU 10.
CPU 10 supplies first frame buffer 20 with one frame of image data, and issues address and control signals to buffer control circuit 25 for controlling the read/write operations of first frame buffer 20. CPU 10 also sends gradation conversion control signals to gradation conversion circuit 30 and sends data for that specifies a write-enable are of second frame buffer 50 and other instructions to write control circuit 40. CPU 10 receives instructions from the operator through keyboard 90. The image data read from first frame buffer 20 is gradation-converted in gradation conversion circuit 30, and is sent to second frame buffer 50 as write data. An existing product, known as a window/level conversion circuit, may be used as gradation conversio

REFERENCES:
patent: 4586038 (1986-04-01), Sims et al.
patent: 4658247 (1987-04-01), Gharachorloo
patent: 4688190 (1987-08-01), Bechtolsheim
patent: 4769713 (1988-09-01), Yasui

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