Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Patent
1996-09-12
1998-10-27
Hjerpe, Richard A.
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
345203, G09G 500
Patent
active
058283846
ABSTRACT:
A VRAM stores a plurality of patterns of image data, an offset register stores values which indicate definition starting positions from which display image data are defined from the plurality of patterns of image data, respectively, a horizontal counter counts dots in a horizontal scanning direction, and a vertical counter counts lines in vertical scanning direction. Address and control signals are successively provided for reading a respective line of the display image data from the VRAM within one horizontal scanning period, based on the values of the offset register and the value of the vertical counter. Each of two second storage devices has a storage capacity for storing a thus-read respective line of the image data. Thus-read image data is written at addresses of a predetermined one of the two second storage devices, the addresses corresponding to displaying dots of the image data, while, according to the value of the horizontal counter, image data stored in the other one of the two second storage devices is read out, where, the image data writing and reading operations are performed alternately between the two second storage devices for each horizontal scanning period.
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Iwasaki Keiichi
Tsukagoshi Toshihiro
Hjerpe Richard A.
Osorio Ricardo
Ricoh & Company, Ltd.
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