Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2000-03-22
2003-05-06
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S003100, C345S003200, C348S446000, C348S448000
Reexamination Certificate
active
06559839
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus and method for displaying images on a matrix display panel such as a liquid crystal display panel.
Liquid crystal display panels are widely used as monitor displays for personal computers and workstations. These monitor display panels are conventionally designed for progressive scanning. Horizontal rows of picture elements or pixels are driven one at a time, in sequence from the top of the display to the bottom. These horizontal rows are referred to below as scan lines. All of the pixels in each scan line are driven simultaneously.
With the advent of multimedia, these computer monitors are being required to display video image signals employing interlaced scanning, in which even fields, comprising only even-numbered scan lines, alternate with odd fields, comprising only odd-numbered scan lines. To enable a progressively scanned monitor panel to display an interlaced image signal, the image signal is conventionally converted from interlaced to progressive scanning by use of a frame memory, or a pair of frame memories, in which the image signal is stored before being displayed. Typically, even fields are stored in one memory area and odd fields in another memory area, and scan lines are read from the two memory areas alternately. The frame memory can also act as a buffer for converting between the scanning rate or frame rate of the received image signal and the possibly different frame rate of the display panel.
A disadvantage of this conventional method is that a frame memory is expensive and takes up space. Moreover, as the resolution of the image signal increases, which is the current trend, the capacity of the frame memory must be increased, making the frame memory even more costly and space-consuming. Use of a frame memory as a buffer for frame-rate conversion is also not entirely satisfactory, as this practice can lead to image defects.
SUMMARY OF THE INVENTION
An object of the present invention is to enable images employing both progressive and interlaced scanning to be displayed on a matrix display panel, without the use of a frame memory.
Another object of the invention is to enable images having a high frame rate to be displayed at a lower frame rate while maintaining high image quality.
A further object of the invention is to reduce electromagnetic noise emissions.
The invented method of displaying an image signal on a matrix display panel comprises the steps of:
determining whether the image signal employs interlaced scanning;
generating a shift signal selecting the scan lines of the matrix display panel one by one in consecutive order;
generating one or more output enable signals enabling the scan lines to be driven when selected;
controlling the output enable signals so that every second selected scan line is driven, if the image signal employs interlaced scanning; and
doubling the frequency of the shift signal, if the image signal employs interlaced scanning.
If the image signal employs progressive scanning, the output enable signals preferably enable every scan line to be driven, unless the frame rate of the image signal exceeds a predetermined frame rate, in which case every second scan line is driven and the scanning system is converted from progressive to interlaced.
The invented image display apparatus has a driver timing generator that generates the shift signal and output enable signals described above. The driver timing generator comprises, for example, a pair of counters and a pair of decoders. The apparatus may also comprise a panel timing generator generating a dot clock signal, and a line memory storing the image data for one scan line at a time. The panel timing generator reads the image data from the line memory in synchronization with the dot clock signal. If the image signal employs progressive scanning and has a frame rate exceeding the predetermined frame rate, the panel timing generator preferably reduces the dot-clock frequency.
Control of the output enable signals allows image signals employing both progressive and interlaced scanning to be displayed without the use of a frame memory.
When the frame rate of the image signal exceeds the predetermined frame rate, each frame is displayed as a field in which only every second scan line is driven. The frame rate is thereby reduced by a factor of two without significant loss of image quality, because image alignment defects do not occur and the field rate is still high enough to avoid flicker. Reducing the dot clock frequency in this case reduces electromagnetic noise.
REFERENCES:
patent: 4908710 (1990-03-01), Wakai et al.
patent: 5091784 (1992-02-01), Someya et al.
patent: 5933196 (1999-08-01), Hatano et al.
patent: 6239779 (2001-05-01), Furuya et al.
patent: 6429836 (2002-08-01), Hansen
patent: 11-164231 (1999-06-01), None
Nishimura Masaru
Someya Jun
Ueno Hiroshi
Birch Stewart Kolasch & Birch
Mengistu Amare
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Jimmy H.
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