Computer graphics processing and selective visual display system – Plural display systems – Diverse systems
Reexamination Certificate
2002-06-03
2004-02-03
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Plural display systems
Diverse systems
C345S671000, C345S213000
Reexamination Certificate
active
06686894
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an image display apparatus and method such as a monitor or a data projector having a matrix display device (hereinafter referred to as a display panel) such as a liquid crystal display panel, a digital micromirror device (DMD), a field emission display (FED), a plasma display panel (PDP), or an LED panel. More specifically, the present invention relates to an image display apparatus and method that displays a scaled-up image if an image size of an input image signal is smaller than a size of an effective display area of the display panel.
FIG. 7
is a diagram showing configuration of a prior art image display apparatus, which is disclosed in Japanese Patent Kokai Publication No. 10-334227 published on Dec. 18, 1998. In the image display apparatus
100
shown in
FIG. 7
, an image signal is supplied from a terminal
101
, and a dot clock SCLK for the image signal is supplied from a terminal
102
. The image signal supplied from the terminal
101
is input to a control unit
103
and a time-base converter
104
. The dot clock SCLK supplied from the terminal
102
is input to the time-base converter
104
. The control unit
103
outputs an output clock DCLK so that a scaled-up image is generated at a frame rate matching a rate at which the input image signal is received. The clock DCLK output by the control unit
103
is supplied to the time-base converter
104
, an interpolation circuit
105
, and a panel controller
106
. Then, the control unit
103
outputs a buffer control signal BANK for controlling a line buffer in the time-base converter
104
. The buffer control signal BANK output by the control unit
103
is supplied to the time-base converter
104
. Moreover, the control unit
103
outputs a modifier signal Q for determining pixel data used for interpolation and a phase value signal PHASE for determining an interpolation coefficient. The modifier signal Q output from the control unit
103
is input to the time-base converter
104
and the interpolation circuit
105
, and the phase value signal PHASE is supplied to the interpolation circuit
105
.
The time-base converter
104
receives the pixel data for the input image in synchronization with the dot clock SCLK, and outputs the received pixel data in synchronization with the output clock DCLK on a different time base according to the buffer control signal BANK supplied from the control unit
103
. The pixel data output from the time-base converter
104
is image data scaled up by copying (or repeating) the pixel data. The scaled-up pixel data output from the time-base converter
104
is supplied to the interpolation circuit
105
. The interpolation circuit
105
performs predetermined interpolation of the pixel data of the scaled-up image, according to the modifier signal Q and the phase value signal PHASE, and outputs the results of interpolation. The pixel data of the scaled-up image subjected to interpolation and output by the interpolation circuit
105
is supplied to the panel controller
106
. The panel controller
106
outputs the scaled-up image subjected to interpolation to the display panel
107
in a signal format compatible with the input interface of the display panel
107
. The display panel
107
therefore displays the scaled-up image subjected to interpolation according to the output of the panel controller
106
.
FIG. 8
is a block diagram showing configuration of a prior art image display apparatus, which is disclosed in Japanese Patent Kokai Publication No. 08-129356 published on May 21, 1996. In the image display apparatus
200
shown in
FIG. 8
, an image signal is input from a terminal
201
. The input image signal is supplied to a first arithmetic circuit
202
and a control unit
203
. The control unit
203
detects resolution of the image data from a synchronizing signal of the image signal and outputs a scaling factor CZ calculated from a ratio of the detected result to the resolution of the display panel
206
. The control unit
203
also outputs a horizontal interpolation control signal CH and a vertical interpolation control signal CV, according to a calculated scaling factor CZ. Moreover, the control unit
203
outputs a memory control signal CM for controlling a write timing and a read timing of the frame memory
204
. The control unit
203
further outputs the display control signal CP for the display panel
206
. The scaling factor CZ output by the control unit
203
is supplied to the first arithmetic circuit
202
and the second arithmetic circuit
205
. The horizontal interpolation control signal CH output by the control unit
203
is supplied to the first arithmetic circuit
202
, and the vertical interpolation control signal CV is supplied to the second arithmetic circuit
205
. The memory control signal CM output by the control unit
203
is supplied to the frame memory
204
. The display control signal CP output by the control unit
203
is supplied to the display panel
206
.
The first arithmetic circuit
202
performs interpolation of the input image data in consecutive dot units, according to the scaling factor CZ and the horizontal interpolation control signal CH, and outputs the image data scaled up in the horizontal direction. The horizontally scaled-up image data output by the first arithmetic circuit
202
is supplied to the frame memory
204
. The frame memory
204
stores the horizontally scaled-up image data of one screen according to the memory control signal CM, and the stored image data is read out. The horizontally scaled-up image data read from the frame memory
204
is input to the second arithmetic circuit
205
. The second arithmetic circuit
205
performs interpolation of the image data of consecutive two lines of the horizontally scaled-up image according to the scaling factor CZ and the vertical interpolation control signal CV. If the scaled-up image data has a lower resolution than the display panel
206
, a display area that has no image data on the display panel
206
is replaced with monochromatic image data. The scaled-up image data output by the second arithmetic circuit
205
is supplied to the display panel
206
. The display panel
206
displays the scaled-up image data according to the display control signal CP and displays monochromatic data in areas without image data.
Owing to the configurations as described above, the above-mentioned prior art image display apparatuses have problems as described below.
FIGS. 9A and 9B
are diagrams for explaining the image display method of the prior art image display apparatus
100
shown in FIG.
7
.
FIG. 9A
shows the numbers (720 pixels wide by 400 pixels high) of horizontal and vertical pixels of the input image signal, and
FIG. 9B
shows the numbers (1024 pixels wide by 768 pixels high) of horizontal and vertical pixels of the displayed image. In this example, a horizontal scaling factor is 1.42 (=1024 pixels/720 pixels), and a vertical scaling factor is 1.92 (=768 pixels/400 pixels). Accordingly, as shown in
FIG. 9B
, vertically distorted (vertically elongated) image is displayed. If the display panel
107
and the input image have different aspect ratios, the prior art image display apparatus
100
shown in
FIG. 7
cannot display a correct scaled-up image with the same aspect ratio as that of the input image.
Unlike the image display apparatus
100
shown in
FIG. 7
, the prior art image display apparatus
200
shown in
FIG. 8
is freed from the impossibility of maintaining the aspect ratio of the input image. However, a frame memory for one screen is needed, which results in very high cost and high difficulty in integrating the signal processing circuit other than display panel into an LSI chip.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a low-cost image display apparatus and method that can display a scaled-up image maintaining the aspect ratio of the input image even if the display panel and the input image have different aspect ratios.
According to the present invention, the image displa
Okuno Yoshiaki
Someya Jun
Birch & Stewart Kolasch & Birch, LLP
Chang Kent
Mitsubishi Denki & Kabushiki Kaisha
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