Image display apparatus

Details Image display apparatus Image display apparatus

2005-06-21

2005-06-21

Eisen, Alexander (Department: 2674)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S100000, C345S209000

Reexamination Certificate

active

06909418

ABSTRACT:
A shift register outputs at a terminal C1to a data register a timing pulse which is active only for one clock in synchronization to the first rise of a clock CLK after a shift signal STH is received as a start pulse, and thereafter outputs timing pulses at terminals C2through C64one after another to the data register. Further, a logical multiplication gate AND2yields the logical multiplication of a Q-output of an SR-type flip flop SRFF3and a superimposed signal, whereby an inversion signal intPOL2is generated. This inversion signal is outputted to the data register. As an OR gate OR1yields the logical addition of an output of a logical multiplication gate AND3and a Q-output of a D-type flip flop DFF64, which causes rising of a superimposed signal of an inversion signal POL2and the shift signal STH which is shifted to a subsequent-stage source driver.

REFERENCES:
patent: 6437766 (2002-08-01), Matsushima et al.
patent: 6525720 (2003-02-01), Baek
patent: 6683596 (2004-01-01), Ozawa
patent: 08-008991 (1996-01-01), None
patent: 10-096888 (1998-04-01), None
patent: 10-149142 (1998-08-01), None

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