Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2001-06-15
2004-03-02
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S099000
Reexamination Certificate
active
06700570
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image display apparatus, such as a liquid crystal display, that converts an analog image signal outputted from a personal computer (hereinafter, referred to as PC), etc., into a digital image signal and displays the resulting image.
2. Description of the Background Art
In the case when an analog input image signal is displayed on an image display apparatus of a digital type such as a liquid crystal display apparatus and a PDP display apparatus, the analog input image signal is converted into a digital image signal through a process in an analog/digital converter (hereinafter, referred to as A/D converter). Here, in the case of the input image signal that is generated by an image-pick up tube such as a TV signal, no problem is raised; however, in the case when the input image signal is a signal that has been obtained by digital/analog converting a signal originally generated as a digital signal, such as an output signal from a PC, it is necessary to pay a special attention to a sampling clock that is used in the A/D converter.
In general, the image signal from a PC is formed by placing an image on a frame memory on a dot basis by the CPU, and the image data is read every reference clock (dot clock) and outputted. In other words, the image data is outputted in synchronism with the dot clock. For this reason, in order to reproduce the image thus formed in a faithful manner by sampling the signal of the image data, it is necessary to generate a sampling clock that has the same frequency as the dot clock and also has an appropriate phase difference from the dot clock.
FIG. 15
is a block diagram that shows a construction of an image display apparatus described in Japanese Patent Application Laid-Open No. 10-149130(1998) as one conventional example of an image display apparatus. In this Figure, reference number
11
is an A/D converter,
12
is a line memory that stores a digital image signal
101
outputted from the A/D converter
11
line by line,
13
is a CPU that carries out writing and reading controls on the line memory
12
and a control on a phase adjusting section
15
,
14
is a timing generation section for generating a writing clock WCK to be sent to the line memory
12
, and
15
is a phase adjusting section for generating sampling clocks
50
and
51
based upon a synchronous signal
52
that is a horizontal synchronous signal of the input signal and a control signal
30
from the CPU
13
.
An analog image signal
100
is converted to a digital image signal
101
by the A/D converter
11
based upon the sampling clock signal
50
outputted from the phase adjusting section
15
. Then, the digital image signal
101
is written in the line memory
12
in accordance with the writing clock WCK that is generated by the timing generation section
14
based upon the sampling clock
51
.
The digital image signal
101
written in the line memory
12
is read from the line memory
12
in accordance with a readout clock RCK outputted by the CPU
13
, and read by the CPU
13
as a signal
20
. The CPU
13
calculates an average value of some image signal levels of digital image signals corresponding to one line that have been read, and compares this with an optimal signal level preliminarily found, and outputs the difference to the phase adjusting section
15
as a differential signal
30
. Thus, the phase adjusting section
15
adjusts the phase of the sampling clocks
50
and
51
by using the differential signal
30
and the synchronous signal
52
.
More specifically, an image signal, which alternately repeats, for example, an image signal level of “white” and an image signal level of “black” every pixel, is used as an analog signal
100
. Therefore, in the case when, for example, an analog/digital converter
11
of 8 bits is used, the outputted digital image signal
101
is allowed to optimally repeat “255” of “white” level and “0” of “black” level for each of R, C and B alternately. Then, the CPU
13
reads from the line memory
12
only either the digital image signal of “white” level or the digital image signal of “black” level alternately written in the line memory
12
, and calculates the average value of the signal levels of the “white” level or the “black” level corresponding to one line. Next, the CPU
13
compares the calculated average value with “255” or “0” that is an optimal signal level, thereby generating a differential signal
30
.
Here, when the sampling clock
50
is adjusted to an optimal phase with respect to the dot clock of the analog video signal
100
, the difference becomes zero; however, when it deviates from the optimal phase, the difference is not zero. For example, as illustrated in
FIG. 16
, in the case when the phase at the reading position of the sampling clock
50
is a, the difference is represented by A. In the same manner, when the phase at the reading position of the sampling clock
50
is b, the difference is represented by B, and when it is c, the difference is represented by C.
In the case when the difference is not zero, the CPU
13
outputs a differential signal
30
corresponding to the value of the difference to the phase adjusting section
15
, thereby controlling the phase adjusting section
15
to make the difference zero. This makes it possible to adjust the phase of the sampling clock
50
to an optimal value with respect to the phase of the analog image signal
100
.
As described above, in the conventional image display apparatus, the image signal, which has been preliminarily determined so as to adjust the phase of the sampling clock, for example, a signal repeating “white” and “black” alternately, needs to be inputted; therefore, the resulting problem is that it is not easy for the user to adjust the phase.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, an image display apparatus comprising an analog/digital converter for converting an analog image signal to a digital image signal by sampling the analog image signal using a sampling clock, a display means for displaying an image by using the digital image signal, differential detection means for detecting a difference in sampling data between continuous two pixels in the digital image signal, a sampling clock generation means for generating the sampling clock by using a synchronous signal of the analog image signal, and adjusting means for adjusting a phase of the sampling clock based upon the difference.
In accordance with the first aspect of the present invention, based upon the difference in the sampling data of continuous two pixels in a digital image signal, the adjusting means adjusts the phase of the sampling clock so that, when an analog image signal is derived from image data that has been stored in unit of pixel and that is read and generated every dot clock, the phase adjustment of the sampling clock is carried out without the necessity of an input signal of a specific pattern.
According to a second aspect of the present invention, the image display apparatus of the first aspect wherein the adjusting means adjusts a phase of the sampling clock so as to make the difference the greatest.
In accordance with second aspect of the present invention, the adjusting means adjusts the phase of the sample clock so as to make the difference the greatest; therefore, it is possible to sample the greatest amplitude section of the signal level that the analog image signal originally owns, and consequently to sample an image signal level that is less susceptible to influences from the rounding.
According to a third aspect of the present invention, the image display apparatus of the first aspect, wherein the adjusting means adjusts a phase of the sampling clock so as to shift to a position having an offset of 180° from a position that makes the difference the smallest.
In accordance with the third aspect of the present invention, the adjustment means adjust the phase of the sampling clock to shift to a position having an offset of 180° from the position that ma
Iwataka Hiroki
Tachibana Miyuki
Birch & Stewart Kolasch & Birch, LLP
NEC-Mitsubishi Electric Visual Systems Corporation
Wu Xiao
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