Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-10-23
2001-06-19
Mengistu, Amare (Department: 2778)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S214000, C345S182000, C345S204000
Reexamination Certificate
active
06249268
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an image display apparatus which uses a display panel or the like formed by PDP (Plasma Display Panel) or LED (Light Emitting Diode), and particularly relates to improvement in controlling a lighting time of pixels within a predetermined time in order to display an image with multiple gradations.
In recent years, an image display apparatus of a flat panel type using PDP or LED has been put into practice, and such a display has been utilized in various fields.
Such an image display apparatus is generally arranged so that an image is displayed with multiple gradations by controlling a time for lighting respective pixels within a predetermined time (1 field period).
FIG. 1
is a block diagram showing an example of the arrangement of such an image display apparatus disclosed in Japanese Patent Application laid-Open No. 6-259033 (1994). This conventional image display apparatus uses PDP, and it includes an A/D converting circuit
12
, frame memories
13
and
14
and a bit selecting circuit
15
. The A/D converting circuit
12
converts a video signal inputted to a video signal input terminal
11
into a digital signal. The video signal, which has been converted into the digital signal by the A/D converting circuit
12
, as image data is written alternately into the frame memories
13
and
14
per predetermined period (for example, {fraction (1/30)} sec or {fraction (1/60)} see which is one frame period). The bit selecting circuit
15
selects image data of pixels (bit) to be displayed from the image data read out alternately from the frame memories
13
and It.
Above conventional image display apparatus also includes a synchronizing signal separating circuit
17
, a timing signal output circuit
18
, an X driver
16
and a Y driver
19
. The synchronizing signal separating circuit
17
separates a synchronizing signal (for example, a horizontal synchronizing signal and vertical synchronizing signal) from the video signal inputted into the video signal input terminal
11
. The timing signal output circuit
18
supplies a timing signal to the A/D converting circuit
12
, the frame memories
13
and
14
, the bit selecting circuit
15
and the other portions based on the synchronizing signal separated by the synchronizing signal separating circuit
17
. The X driver
16
is supplied with the image data selected by the bit selecting circuit
15
and the timing signal from the timing signal output circuit
18
, and outputs pulse signals for deleting, writing, addressing, scanning, sustaining (discharge sustaining), etc. to a matrix-type display panel
20
which is a PDP. The Y driver
19
is supplied with the timing signal from the timing signal output circuit
18
, and outputs a pulse signal for scanning to the display panel
20
.
The following describes an operation of the image display apparatus having such an arrangement.
A video signal inputted to the video signal input terminal
11
is converted into a digital signal by the A/D converting circuit
12
so that odd frames and even frames are written as image data alternately into the frame memories
13
and
14
per predetermined period. The bit selecting circuit
15
reads out the image data alternately from the frame memories
13
and
14
, and selects the image data of pixels to be displayed so as to supply it to the X driver
16
.
The X driver
16
outputs respective pulse signals for deleting, writing, addressing, scanning, sustaining, etc. based on the image data from the bit selecting circuit
15
and a timing signal from the timing signal output circuit
18
, and performs matrix display on the display panel
20
according to the pulse signal for scanning outputted by the Y driver
19
.
For example, in the case of 8-bit gradation (256 gradations) display, as shown in
FIG. 2
, as for the pixels of the matrix display panel
20
, one field period as one picture display period is divided into eight subfield periods SFI, SF
2
, . . . SFt
8
, and the divided subfield periods SF
1
, SF
2
, . . . SF
8
are further divided respectively into an addressing periods AP and display periods SP. The respective subfield periods SFl, SF
2
, ... SF
8
are weighted in proportion of 1:2:4: . . . :128, and when a display pulse number for weight per unit (sustain pulse: pulse for sustaining plasma discharge) is two, for example, respective display pulse numbers of the subfield periods SF
1
, SF
2
, . . . SF
8
becomes two, four, eight, . . . 256.
Since the display pulse number is approximately in proportion to luminous brightness of the pixels, when subfield periods (for example, SF
1
, SF
3
and SF
5
) are selected from the eight subfield periods SF
1
, SF
2
, . . . SF
8
according to the luminous brightness, the pixels can be lit for a time while gradation display (for example, the eighth-gradation display in the 256-gradation display) can be obtained according to the luminous brightness in the 256 gradations. Here, the addressing periods AP of the respective subfield period SF
1
, SF
2
. . . SF
8
are constant (for example, 1.5 ms) regardless of the subfield periods, and are determined by a type of the display panel
20
. In the addressing period AP of each subfield period, writing is performed on the whole surface (all pixels) of the display panel
20
, and deleting discharge takes places according to image data and thus addressing is performed. In the display period SP next to the addressing period AP, as mentioned above, the pixels are lit or turned off for the time while each subfield period is weighted according to a display pulse number (sustain frequency).
This conventional image display apparatus controls the time for lighting the pixels within a predetermined period (for example, {fraction (1/30)} sec or {fraction (1/60)} sec which is one field period) according to a display pulses number (sustain frequency) so as to display an image with multiple gradations.
FIG. 3
is a block diagram showing a principle of an image display apparatus disclosed in Japanese Patent Application Laid-Open No. 9-244575 (1997).
This conventional image display apparatus includes a matrix type display panel
31
which is PDP, brightness setting means
33
, display rate detecting means
32
and translation table selecting means
34
. The brightness setting means
33
converting a video signal into a digital signal so as to generate image data, and sets brightness per pixel (bit) of the image data. The display rate detecting means
32
detects a display rate DR (the ratio of the sum of values obtained by multiplying a number of pixels on the whole picture to be lit by the lighting time to the maximum value) on one display picture of the display panel
31
from the image data. The translation table selecting means
34
selects a translation table for correcting and translating the brightness set by the brightness setting means
33
according to the display rate DR detected by the display rate detecting means
32
, and corrects and translates the brightness so that the power consumption of the display panel
31
does not become excessive.
The translation table of the translation table selecting means
31
is made based on the display rate DR which is previously measured so that the power consumption of the display panel
31
does not become excessive.
This conventional image display apparatus further includes sustain frequency determining means
35
for determining a display pulse number (sustain frequency) according to the brightness which has been corrected and translated by the translation table selecting means
34
so as to supply the display pulse number to the display panel
31
.
In the conventional image display apparatus having such an arrangement, the brightness per the pixels of the image data set by the brightness setting means
33
is corrected by the translation table selecting means
34
based on the display rate DR detected by the display rate detecting means
32
so that the power consumption of the display panel
31
does not become excessive. Then, the sustain frequency determining
Tachibana Miyuki
Yoshioka Kazuo
Mengistu Amare
Mitsubishi Denki & Kabushiki Kaisha
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