Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2002-06-07
2004-06-29
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S089000, C345S098000, C345S100000, C345S690000
Reexamination Certificate
active
06756962
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a liquid crystal image display that can display high quality images in particular.
BACKGROUND ART
A circuit diagram of an offset canceling buffer for a low-temperature poly-Si TFT panel drive circuit in a conventional liquid crystal image display is illustrated in FIG.
13
. This circuit cancels the offset voltage of the output of a differential amplifier
115
that comprises the buffer. As a consequence, luminance non-uniformity of vertical streaks on a liquid crystal panel due to variations in the offset voltages of a plurality of buffers in the liquid crystal image display can be prevented. Variations in the offset voltages among the buffers are caused by a great variation in the device performance of low-temperature poly-Si TFTs that constitute positive and negative (inverted) inputs of the differential amplifier
115
, as compared with single-crystal MOS transistors.
Referring to
FIG. 13
, an analog input signal input to an input terminal Vin is supplied to an image pixel area (not shown), in the form of an analog output from an output terminal Vout via the differential amplifier
115
being given a negative feedback. The offset canceling circuit comprises a capacitance
151
, switches
152
,
153
, and
154
, a negative feedback loop that passes through the switch
152
and the capacitance
151
, and a wire that extends from a point between the switch
152
and the capacitance
151
to be connected to the input terminal Vin via the switch
154
.
An operation associated with
FIG. 13
will be described below. In the first half of a horizontal scanning period, the switches
153
and
154
are turned on, and the switch
152
is turned off. At this point, the offset voltage of the output of the differential amplifier
115
is stored in the capacitance
151
. Then, in the second half of the horizontal scanning period, the switches
153
and
154
are turned off, and the switch
152
is turned on. Since the capacitance
151
that stores the offset voltage of the differential amplifier
115
is inserted in series into the negative feedback loop as a result of this operation, the offset voltage is subtracted within the differential amplifier
115
. It means that the offset voltage is canceled.
This conventional art is described in detail in IEICE Technical Report Electronic Information Displays 98-125, January 1999, for example.
DISCLOSURE OF THE INVENTION
According to the conventional art described above, the offset voltage caused by a mismatch of the differential amplifier using polycrystalline Si TFTs can be canceled. However, if switches in the offset canceling circuit are composed of polycrystalline Si TFTs, the switch
153
causes a variation among the offset voltages of a plurality of offset canceling buffers in a liquid crystal image display.
This will be described below with reference to FIG.
14
.
FIG. 14
is a diagram where reference characters necessary for the description are added to the circuit diagram of the offset canceling buffer illustrated in FIG.
13
. Cm denotes a capacitance value of the capacitance
151
, Cp denotes a capacitance value of a parasitic capacitance
155
for a inverted input terminal of the differential amplifier
115
, a node A denotes the inverted input terminal of the differential amplifier
115
, q
1
and q
2
denote feed-through charges resulting from turning off of the switch
153
, and G denotes the open-loop gain of the differential amplifier
115
.
In the offset canceling operation, after storing the offset voltage of the differential amplifier
115
in the capacitance
151
, when turning off the switches
153
and
154
, the TFTs that comprise the respective switches emit feed-through charges to their respective source and drain terminals. As a result of this, the feed-through charge q
1
modulates the amount of charges stored in the node A. This modulation occurs irrespective of an order in which the switches
153
and
154
are turned off. The feed-through charge q
2
of the switch
153
has no appreciable effect on the modulation. Incidentally, the modulation of the amount of charges stored in the node A by the feed-through charge of the switch
154
can be avoided by turning off a head of the switch
153
.
The modulation of the amount of charges stored in the node A causes an additional offset voltage &Dgr; Vout expressed by Equation (1) to the output terminal Vout of the offset canceling buffer.
&Dgr;
Vout=−G/
(
G·Cm+Cp+Cm
)
·q
1
Equation (1)
Generally, the open-loop gain G of the differential amplifier
115
is designed to be an exceedingly large value. However, even if the open loop gain G is approximated as an infinite value, the offset voltage &Dgr; Vout of (−q
1
/Cm) is generated, as determined by Equation (1).
Then, this offset voltage &Dgr; Vout varies among a plurality of offset canceling buffers in the liquid crystal image display according to the following reason.
Since the buffer is provided for an impedance reduction, it is not preferable that input impedance is designed to be small, so that the capacitance Cm of the capacitance
151
cannot be designed to be so large. Consequently, the influence of the switch feed-through charge q
1
generated when the switch
153
is turned off will become great.
When a single-crystalline MOS transistor is employed as a switch, a variation in a threshold voltage Vth of the switch is in general at most approximately 20 mV, and the gate dimensions are of the order of submicrons. However, in the case of a polycrystalline Si TFT, its channel comprises a crystalline grain structure, and a surface of a gate insulation film is not stabilized, so that the Vth sometimes ranges from several hundred millivolts to nearly one volt at most. In addition, since the dimensions of a substrate of the low-temperature poly-Si TFT is comparatively large, ranging from several ten centimeters to one meter, the dimensions of the processed gate are of the order of at least several microns. Accordingly, variations of processing are comparatively large.
The feed-through charge q
1
mainly comes from a channel charge Cg·(Vg−Vth), in which Cg denotes a gate capacity determined by the area of the gate, the thickness of the gate insulation film, and the dielectric constant of the gate insulation film. Accordingly, variations of the Vth and the area of the gate affect the variation of the feed-through charge q
1
, and as a result make variations of the offset voltages &Dgr; Vout among the offset canceling buffers.
Assuming a variation of the threshold voltage Vth is 1V, Cm is 100 times of the channel capacity of the switch
153
, and q
1
is a half of the channel charge of the switch
153
, for example, a variation of the offset voltage &Dgr; Vout is larger than 5 mV at the outputs of the offset canceling buffer, even if the open-loop gain G of the differential amplifier is assumed to be infinite. Further, a variation of the area of the gate is added to the above-mentioned variation, so that a variation in the offset voltage &Dgr; Vout becomes larger than 5 mV. Thus, this offset canceling circuit is impractical.
Incidentally, here, a problem existing in the conventional offset canceling circuit is explained, as a problem caused by the switch
153
. This is not a specific problem for the circuit illustrated in
FIG. 14
, but is a common problem for offset canceling circuits in general. In the offset canceling circuit, an offset voltage stored in a capacitance in advance is added to an input to the differential amplifier for subtracting it. For this purpose, it is necessary that one end of the capacitance is connected to the input terminal of the differential amplifier. Further, to write the offset voltage in the capacitance, the above-mentioned end of the capacitance must be connected to a switch simultaneously. So that, theoretically, a feed-through charge at the time of this switch being turned off is applied to the input of the differential amplifier through the capacitance as a voltage. Even if the switch is com
Akimoto Hajime
Mikami Yoshirou
Dinh Duc Q.
Liang Regina
Miles & Stockbridge P.C.
LandOfFree
Image display does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Image display, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Image display will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3310253