Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2001-06-18
2004-03-09
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S003300
Reexamination Certificate
active
06704009
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital image display for converting an analog input video signal to a digital signal, performing signal processes such as pixel conversion on the digital signal, and transmitting the resultant signal to a display unit.
2. Description of the Background Art
For example, in an image display using a liquid crystal panel, a display unit as the liquid crystal panel portion requires a digitized video signal (digital video signal). Consequently, when a video signal supplied to such a digital image display is an analog signal, the analog video signal has to be A/D (analog-to-digital) converted. An example of the analog video signal which is supplied to the digital image display is a video output signal of a current personal computer or the like.
A sampling clock used at the time of the A/D conversion is generated from a vertical synchronizing signal and a horizontal synchronizing signal which are either included in the input analog video signal or extracted from the input analog video signal and separately supplied. Usually, the sampling clock is generated so that its frequency coincides with the frequency of a dot clock (clock specifying the period of a dot, used by a personal computer or the like to generate a video signal as a dot train) specifying the size of one pixel (dot) in the analog video signal.
The video signal converted to the digital signal is subjected to signal processes such as pixel conversion and picture quality adjustment before it is supplied to the display unit.
The pixel conversion denotes a process of enlarging or reducing an image, which is performed when the resolution (expressed by dots×lines) of the input analog video signal and that of the display unit do not coincide with each other. For example, when the resolution of the input analog video signal is 640 dots×480 lines and the resolution of the display unit is 1024 dots×768 lines, a process of enlarging an image (pixel conversion) by 1024/640 times in the horizontal direction and by 768/480 times in the vertical direction is performed on the input analog video signal and the resultant signal is transmitted to the display unit. As a result, the image is displayed fully on the screen of the display unit of 1024 dots×768 lines.
When the sampling clock used at the time of sampling the input analog video signal is used as it is at the time of the pixel conversion and the digital video signal is transmitted to the display unit, only data of the pixel amount of 640 dots×480 lines can be transmitted. In order to enable the data of the pixel amount of 1024 dots×768 lines to be transmitted to the display unit, it is necessary to newly generate a data clock of a frequency different from that of the sampling clock, which is adapted to the resolution of the display unit (that is, for specifying the resolution after the pixel converting process) and transmit the digital video signal by using the data clock to the display unit. As described above, in the digital image display, two kinds of clock signals (sampling clock and data clock) of different frequencies are used in the video signal process.
There are cases where noise occurs in the input analog video signal. When the noise has a component synchronized with the data clock, at the time of processing the digital video signal and transmitting the processed signal to the display unit, the noise component is also sampled and interference of stripes or the like, that is, what is called beat noise (regular noise) appears on the display screen. When the two kinds of clock signals of different frequencies as described above are generated in the proximity of one chip, the different clock frequencies interfere with each other and beat interference is apt to occur.
Obviously, the beat interference can be generally solved by separating an analog signal processing unit (A/D converter in the above example) from a digital signal processing unit. However, as the integration density of an IC (Integrated Circuit) increases, the analog signal processing unit and the digital signal processing unit are realized in a single IC. It is therefore difficult to separate the analog video signal processing unit from the digital video signal processing unit.
An example of an image display capable of suppressing occurrence of beat noise is disclosed in Japanese Patent Application Laid-Open No. 9-244586 (1997).
FIG. 8
shows the configuration of the technique. Shown in
FIG. 8
are a synchronization separating circuit
101
for separating a sync signal from a video input signal, a first phase comparator
102
, a first LPF (Low Pass Filter)
103
, a first VCO (Voltage Controlled Oscillator)
104
, and a first counter
105
. The first phase comparator
102
, first LPF
103
, first VCO
104
, and first counter
105
construct a first PLL (Phase Locked Loop)
106
.
Also shown in
FIG. 8
are a pixel converting circuit
107
for enlarging or reducing an image, a second phase comparator
108
, an adder
109
, a second LPF
110
, a second VCO
111
, and a second counter
112
. The second phase comparator
108
, adder
109
, second LPF
110
, second VCO
111
, and second counter
112
construct a second PLL
113
.
Also shown in
FIG. 8
are a timing generating circuit
114
for receiving a clock output from the second PLL
113
and generating various timings, a first frequency divider
115
for frequency-dividing a horizontal sync signal, a second frequency divider
116
for frequency-dividing a vertical sync signal, and an exclusive OR gate
117
for performing an exclusive OR operation on outputs from the first and second frequency dividers
115
and
116
.
According to the technique, a composite video input signal supplied from the outside is supplied to the pixel converting circuit
107
. The pixel converting circuit
107
performs the process of enlarging or reducing the video input signal by using a clock from the first PLL
106
(which is an output from the first VCO
104
and corresponds to the sampling clock) and a clock from the second PLL
113
(which is an output from the second VCO
111
and corresponds to the data clock).
By adding a voltage of a predetermined volume to the VCO control voltage of the second PLL
113
for generating a clock at the post stage every toggle cycle as the exclusive OR of the horizontal and vertical cycles, the video signal is modulated. That is, noise is added to an image in which beat interference is apt to appear, thereby making regular interference inconspicuous.
As noise is added to an image, however, the method as described above has a problem such that other adverse influences such as phase deviation (jitter) are apt to be exerted on the image.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided an image display having: an A/D converting unit for receiving an analog video signal and sampling the analog video signal by using a sampling clock, thereby converting the analog video signal into a first digital video signal; a signal processing unit for performing a pixel converting process on the first digital video signal by using a data clock for specifying resolution after the pixel converting process to thereby generate a second digital video signal; a display unit for receiving the second digital video signal and displaying an image; and a control unit for controlling generation of the sampling clock and generation of the data clock, wherein a frequency of the data clock is preset for each kind of the analog video signal, and the control unit selects the frequency of the data clock on the basis of the presetting at the time of controlling the generation of the data clock.
According to a second aspect of the invention, in the image display, the analog video signal is supplied as a dot train, and a frequency of a dot clock for specifying a period of the dot train of the analog video signal and a frequency of the data clock are set so that one of the frequencies does not become an integral mu
Iwataka Hiroki
Tachibana Miyuki
Birch & Stewart Kolasch & Birch, LLP
NEC-Mitsubishi Electric Visual Systems Corporation
Wu Xiao
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