Coded data generation or conversion – Digital code to digital code converters
Patent
1996-04-11
1998-04-07
Gaffin, Jeffrey A.
Coded data generation or conversion
Digital code to digital code converters
H03M 700
Patent
active
057369445
ABSTRACT:
A decoding output of a B-picture is given to a memory. A memory control circuit divides a one (1) image plane to four (4) regions. Write is executed to the memory for the divided image data that are the decoding output with respect to eight (8) regions of first and second fields. The time at which each of the divided image data are retained in the memory is decided in accordance with the field to which the divided image data belongs and a position on an image plane. On the basis of this, subsequent to the readout of the divided image data, the other divided image data are written to a common storage region of the memory. Thus, a total memory capacity is reduced to enable interlacement conversion.
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patent: 5146325 (1992-09-01), Ng
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patent: 5539466 (1996-07-01), Igrashi et al.
P1394 Standard for a High Performance Serial Bus, IEEE Standards, P1394 Draft 8.0v4, Nov. 21, 1995, (Complete Copy with relevant pages circled in Table of Contents).
Kunzman et al., "1394 High Performance Serial Bus: The Digital Interface for ATV", Reprinted with Permission of the IEEE, presented at the International Conference on Consumer Electronics, Chicago, ILL. Jun. 1995.
Hoffman et al., "IEEE 1394: A Ubiquitous Bus", Presented at COMPCON Spring 1995, San Francisco, CA.
Gaffin Jeffrey A.
Jean-Pierre Peguy
Kabushiki Kaisha Toshiba
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