Facsimile and static presentation processing – Facsimile – Facsimile system interface
Reexamination Certificate
1999-11-09
2002-12-03
Wu, Jingge (Department: 2723)
Facsimile and static presentation processing
Facsimile
Facsimile system interface
C345S543000, C345S547000, C345S556000
Reexamination Certificate
active
06490058
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image decoding and display device for decoding compressed image data based on MPEG (Moving Picture Experts Group) and then displaying the decoded image data on a monitor.
2. Description of the Related Art
MPEG (Moving Picture Experts Group) method is a typical technique for synthetically handling audio data and image data in the multimedia field, and the MPEG method are widely applied to various communication applications.
A MEPG system has following function:
A stream of MPEG video data is synchronization with a stream of MPEG audio data (both data that have been encoded) in order to integrated them; and
The integrated data are then converted to data having a data format that is applicable to an inherent physical format and a protocol to be used in recording mediums and networks.
For example, in the image data processing in a MPEG video decoder, a video stream that has been encoded in 24 frame/second is decoded in 30 frame/second. A 3:2 pull down display processing is also necessary in order to display the decoded video stream on a monitor.
When one frame is displayed on a monitor in the 3:2 pull down display processing, three fields (3 fields) and two fields (2 fields) must be displayed alternately.
Since the conventional image decoding and display device has the configuration and the function described above, it is necessary to incorporate a memory whose memory size is three frames when the pictures of three fields to be displayed are decoded image data of a B picture (Bi-directionally predicted picture). In other words, the conventional image decoding and display device must incorporates an additional memory region of three frames when the 3:2 pull down display processing is performed based on the MPEG method. This increases the size of the conventional image decoding and display device.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide an image decoding and display device capable of reducing a memory size of a bank in a frame memory to store a B picture without increasing a decoding performance and capable of realizing a vertical reduction filter function.
In accordance with a preferred embodiment of the present invention, an image decoding and display device comprises a control section, an image decoding section, a frame memory, a frame memory interface, and a video interface. The control section controls the entire operation of the image decoding and display device. The image decoding section inputs encoded image data transferred from outside of the image decoding and display device, and decodes the encoded image data under the control by the control section, and generates decoded image data. The frame memory comprises banks, a memory size of each of which is one frame for storing the decoded image data, and a bank made up of a plurality of sectors and whose memory size is not less than 0.5 frame for storing the decoded image data of a frame B. The frame memory interface inputs the decoded image data outputted from the image decoding section according to the control of the control section, writes the decoded image data into the frame memory, and reads the decoded image data stored in the frame memory. The video interface inputs the decoded image data transferred from the frame memory interface, converts the decoded image data in format, and outputs the decoded image data converted to outside. In the image decoding and display device described above, under a fixed mapping mode by the control of the control section, the frame memory interface writes the decoded image data into predetermined sectors in the frame memory, and under a dynamic mapping mode by the control of the control section, the frame memory interface refers a sector information table that shows the use state of each of the plurality of sectors in the frame memory in order to search unused sector, and allocates the unused sector when the frame memory interface writes the decoded image data into the frame memory, and release the used sector when decoded image data are read.
In the image decoding and display device as another preferred embodiment of the present invention, the frame memory consists of a bank
0
, a bank
1
, and a bank
2
, and a memory size of each of the bank
0
and the bank
1
is one frame in which the decoded image data of one frame are stored, and the bank
0
and the bank
1
store I/P frames to be used as reference image data. In the image decoding and display device described above, a memory size of the bank
2
is not less than 0.5 frame, and the bank
2
is divided into the plurality of sectors, and each sector in the bank
2
stores the decoded image data of the frame B.
In the image decoding and display device as another preferred embodiment of the present invention, when the frame memory interface performs the management of the bank
2
in the frame memory under the fixed mapping mode and decoded image data of both two frames are stored in the frame memory simultaneously, the frame memory interface controls so that the decoding process by the image decoding section is temporarily halted while observing display lines.
In the image decoding and display device as another preferred embodiment of the present invention, when the frame memory interface performs the management of the bank
2
in the frame memory under the dynamic mapping mode, the frame memory interface searches unused sectors in the bank
2
while referring the sector information table when a sector allocation instruction for the sectors in the bank
2
by the frame memory interface is activated, writes the decoded image data into the unused sector searched, and releases the sector in the bank
2
after the decoded image data in the sector are read.
In the image decoding and display device as another preferred embodiment of the present invention, the frame memory consists of a bank
0
, a bank
1
, and a bank
2
, and a memory size of each of the bank
0
and the bank
1
is one frame in which the decoded image data of one frame are stored, and the bank
0
and the bank
1
store I/P frames to be used as reference image data, and a memory size of the bank
2
is one frame, and the bank
2
is divided into the plurality of sectors, and each sector in the bank
2
stores the decoded image data of the frame B, and in order to execute a 3:2 pull down processing for decoded image data of a frame for continuously displaying during three field time lengths under the dynamic mapping mode, the frame memory interface controls the operation of the frame memory so that a sector releasing instruction is not activated only during a first display time in the three field time lengths for continuously displaying the decoded image data of the frame.
In the image decoding and display device as another preferred embodiment of the present invention, a memory size of the bank
2
is not less than one fields and less than two fields, and in order to execute a 3:2 pull down processing for decoded image data of a frame for continuously displaying during three field time lengths under the dynamic mapping mode, the frame memory interface controls the operation of the frame memory so that a sector releasing instruction is not activated only during a second display time in the three field time lengths for continuously displaying the decoded image data of the frame.
In the image decoding and display device as another preferred embodiment of the present invention, the frame memory consists of a bank
0
, a bank
1
, and a bank
2
, and a memory size of each of the bank
0
and the bank
1
is one frame in which the decoded image data of one frame are stored, and the bank
0
and the bank
1
store I/P frames to be used as reference image data, and a memory size of the bank
2
is not less than one field, and the bank
2
is divided into the plurality of sectors, and each sector in the bank
2
stores the decoded image data of the frame B. Further, in or
Ohkawahara Ryohei
Takabatake Akihiko
Burns Doane , Swecker, Mathis LLP
Wu Jingge
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