Image decoder with bus arbitration circuit

Details Image decoder with bus arbitration circuit Image decoder with bus arbitration circuit

1996-02-05

1998-08-11

Bayerl, Raymond J.

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

345501, G06F 1300

Patent

active

057933847

ABSTRACT:
An image decoder has a bus arbitrating circuit for controlling the use of the bus by any one of input bit stream buffer control circuit, decoding circuit, and image output control circuit. The bus arbitrating circuit controls the bus to provide the image output control means with the highest priority to use the bus without interruption to access the memory at predetermined time intervals. After the completion of the memory access by the image output control means, the bus arbitrating circuit detects whether a request for access to the memory is made by the input bit stream buffer control circuit, and when the request is made, permits the input bit stream buffer control circuit to use the bus. When both the image output control circuit and input bit stream buffer control circuit are not using the bus, permits the decoding means to use the bus to access the memory.

REFERENCES:
patent: 4941193 (1990-07-01), Barnsley et al.
patent: 5369744 (1994-11-01), Fukushima et al.
patent: 5555322 (1996-09-01), Terai et al.
patent: 5566254 (1996-10-01), Murata et al.

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