1998-01-14
2000-02-01
Evans, Arthur G.
395114, G06H 1500
Patent
active
060212608
ABSTRACT:
In the present invention, predetermined lower bits of address data outputted to a page memory form a base section through a system address bus, a bus conversion section, and a general purpose address bus. In addition, other address data than the predetermined lower bits is supplied the page memory through the system address bus and the bus conversion section. Address data outputted from the base section to the general purpose bus device is supplied thereto through the system address bus, the bus conversion section, and the general purpose address bus.
REFERENCES:
patent: 5687296 (1997-11-01), Shimada
patent: 5727136 (1998-03-01), Kubota
Yasunobu; "Bus Conversion Circuit"; Patent Abstracts of Japan; Publication No. 04 246947; Publication Date: Sep. 2, 1992; Vol 017, No. 019 (E-1306); (Jan. 13, 1993).
Evans Arthur G.
Kabushiki Kaisha Toshiba
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