Image data parallel processing apparatus

Details Image data parallel processing apparatus Image data parallel processing apparatus

1995-03-27

1997-12-23

Harvey, Jack B.

Boots, shoes, and leggings

3649207, 36423782, 358514, 382304, G06F 1500

Patent

active

057015058

ABSTRACT:
One page of image data is divided into six data streams of blocks data. First to sixth FIFO memories of a speed difference absorbing circuit absorb a difference between a transfer rate of the block data and a processing speed of the subsequent circuits. FIFO memories of a line delay circuit delay the respective block data such that delay times for the respective block data change step by step by a predetermined time. An order conversion circuit produces 4-line parallel image data by sequentially selecting the block data sent from the line delay circuit. Sync signals for the four respective lines are delayed step by step by a predetermined time.

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