Computer graphics processing and selective visual display system – Computer graphics processing – Attributes
Reexamination Certificate
1998-12-21
2003-03-04
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Computer graphics processing
Attributes
C345S001100, C345S003100, C345S030000, C345S087000, C345S213000, C345S502000, C345S603000, C348S441000, C348S443000, C348S220100, C348S449000, C348S555000
Reexamination Certificate
active
06529205
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image display apparatus which displays an image data stored in a frame memory of a computer apparatus. More particularly, the present invention relates to an image display apparatus which a signal with a RGB format stored in an information processing apparatus is converted and displayed into an NTSC signal.
2. Description of the Related Art
Conventionally, an image data in the form of bit map is stored in a frame memory which is composed of a dual port memory and a display control is performed to the image data. When such an image data in the form of bit map is converted into an NTSC signal to display on an NTSC display unit such as a home television unit, an exclusive use memory is needed for the NTSC display. However, there is a problem in the cost and the improvement is wanted.
FIG. 1
is a block diagram illustrating the structure of a conventional example.
A drawing processor
11
is connected with a frame memory
12
and a frame memory control unit
13
. A display timing control unit
14
gives a timing signal to the frame memory control unit
13
such that a display data is read out from the frame memory
12
. The read out display data is supplied to a digital-to-analog (D/A) converter
15
. The digital-to-analog converter
15
converts the display data in a digital form into the display data in an analog form, to output as an RGB signal to a CRT (cathode-ray tube) display unit
16
in response to a timing signal supplied from the display timing control unit.
Also, the display data read out from the frame memory
12
is supplied to an NTSC frame memory
19
. The display data is outputted from the NTSC frame memory
19
in response to a timing signal supplied from the display timing control unit
14
, and is supplied to an NTSC converting unit
17
. The NTSC converting unit
17
converting the display data into an NTSC signal such that the NTSC signal is displayed on an NTSC display unit
18
.
As described above, when an image data stored in the frame memory composed of a dual port memory should be displayed on the NTSC display unit, an exclusive use frame memory is needed for the NTSC display.
Also, the region of the image data which can be displayed on the NTSC display unit is limited. Therefore, when an image data should be displayed on both the CRT display unit and the NTSC display unit, the image display apparatus has become expensive.
In addition, an image signal converting apparatus is described in Japanese Laid Open Patent Application (JP-A-Heisei 3-184086). In this reference, an RGB signal in the form of interlace is displayed on a computer display unit after it stored in an image memory. The RGB signal read out from the image memory is stored in one of field memories. Then, the RGB signal is read out and stored in a line memory. As a result, an output signal from the line memory is subjected to D/A conversion and encoded into an NTSC display signal.
SUMMARY OF THE INVENTION
The present invention is accomplished to solve the above problems. Therefore, an object of the present invention is to provide an image display apparatus in which when a dual port memory is used as a frame memory, an exclusive use frame memory is not needed for NTSC display.
Another object of the present invention is to provide an image display apparatus in which the whole of an image data stored in a frame memory can be displayed on a CRT display unit and a part of the image data for a rectangular region can be displayed on an NTSC display unit.
In order to achieve an aspect of the present invention, an image data display apparatus includes a terminal display unit, an NTSC display unit, and a frame memory having a first port and a second port, for storing an image data. A display timing control unit generates a terminal display timing signal and an NTSC display timing signal. A frame memory control unit generates a first read control signal in response to the terminal display timing signal such that the image data is read out from the first port of the frame memory, and a second read control signal in response to the NTSC display timing signal such that at least a part of the image data is read out from the second port of the frame memory. A first converting unit converts the image data read out from the first port of the frame memory into a terminal display signal such that the read out image data is displayed on the terminal display unit. Also, a second converting unit converts the at least a part of the image data read out from the second port of the frame memory into an NTSC display signal such that the at least a part of the image data is displayed on the NTSC display unit.
The frame memory desirably has a serial port as the first port and a random port as the second port. Also, the second converting unit desirably includes a buffer for storing the at least a part of the image data.
In the above, the at least a part of the image data is in a specified rectangular region. The image data display apparatus may further include a designating unit for specifying the specified rectangular region. Thus, the frame memory control unit generates the second read control signal in response to the NTSC display timing signal based on the specified rectangular region.
The image data display apparatus may further includes a processing unit for performing predetermined processing to the at least a part of the image data to transfer to the second converting unit.
In order to achieve another aspect of the present invention, a method of displaying an image data, includes the steps of:
generating a terminal display timing signal and an NTSC display timing signal;
generating a first read control signal in response to the terminal display timing signal to read out an image data from a first port of a frame memory;
generating a second read control signal in response to the NTSC display timing signal to read out at least a part of the image data from a second port of the frame memory;
performing first conversion of the read out image data into a terminal display signal such that the read out image data is displayed on a terminal display unit; and
performing second conversion of the at least a part of the image data read out into an NTSC display signal such that the at least a part of the image data is displayed on an NTSC display unit.
In order to still another aspect of the present invention, an image data display apparatus includes a frame memory, a terminal display unit, and an NTSC display unit, a generating section for generating a terminal display timing signal and an NTSC display timing signal, a first control signal generating section for generating a first read control signal in response to the terminal display timing signal to read out an image data from a first port of the frame memory, a second control signal generating section for generating a second read control signal in response to the NTSC display timing signal to read out at least a part of the image data from a second port of the frame memory, a first converting section for performing first conversion of the read out image data into a terminal display signal such that the read out image data is displayed on the terminal display unit, and a second converting section for performing second conversion of the at least a part of the image data read out into the NTSC display signal such that the at least a part of the image data is displayed on an NTSC display unit.
REFERENCES:
patent: 5276436 (1994-01-01), Shaw et al.
patent: 5301017 (1994-04-01), Murakami
patent: 5353063 (1994-10-01), Yagisawa et al.
patent: 5519825 (1996-05-01), Naughton et al.
patent: 5790113 (1998-08-01), Perlman et al.
patent: 6008795 (1999-12-01), Nakamura
patent: 6154225 (2000-11-01), Kou et al.
patent: 3-184086 (1991-08-01), None
Kovalick Vincent E.
Sughrue & Mion, PLLC
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