Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
1998-12-21
2001-12-11
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S505000, C345S173000, C345S179000
Reexamination Certificate
active
06329995
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to an image creation apparatus, particularly to the acceleration of the drawing input processing.
PRIOR ART
With respect to image creation apparatuses, acceleration of input processing for drawing data has been demanded, but it has become difficult as resolution has improved. Since the amount of processing necessary for drawing data processing is in proportion to the resolution squared, image memories for low resolution and high resolution are provided. Drawing data is processed at low resolution for the time being, displayed on a monitor, and is also processed at high resolution concurrently. A high resolution image is displayed after processing. During the process, real-time processing at low resolution and image quality at high resolution are maintained. The processing at low resolution is effective in case the processing at high resolution is delayed from drawing input.
However, demand for image quality has increased, and multiple concurrent processing with the high resolution for drawing input has been in need. The inventor considered an apparatus shown in
FIGS. 5-7
as an example of concurrent processing. In the example in
FIG. 5
, the drawing position is specified to the image on a monitor by a digitizer and so on, received at a sequencer
2
, and is organized at a queue and so on. Then, a patch is divided into four, for example, and concurrent processing is carried out. Density data generators
4
-
1
to
4
-
4
for the brush used for drawing and multipliers
6
-
1
to
6
-
4
are placed in series at each drawing pipeline. High-speed access to an area RAM
10
is executed by a barrel shifter
8
, and processing for a patch is carried out. After processing is finished for a patch, the next patch is divided into four and processed. After processing is finished for a stroke, the high resolution image stored in a file memory
14
and an input image stored in the area RAM
10
are blended by a linear interpolator
12
. As described, the principle of drawing is to process a plurality of patches one by one in order. Processing data for pixels within a patch is read out from the area RAM
10
, multiplied by the data of the density data generator
4
by the multiplier
6
, and is rewritten into the area RAM
10
. Since the plurality of patches overlap with each other, recursive operation for the same pixels at the area RAM
10
is carried out.
The division of patches is shown in
FIG. 6
, and each patch p
1
-p
3
is divided into four. In
FIG. 6
, the processing for a patch p
1
is already executed and the processing for a patch p
2
is being carried out. The patch p
2
is divided into areas p
2
-
1
to p
2
-
4
shown at the bottom of the figure. Processing is completed up to area
16
, while area
18
is yet to be processed in each area.
Processing for a stroke comprising patches p
1
-pn is shown in FIG.
7
. Providing that four drawing pipelines are included, each patch is divided into four. The first area is processed at the first pipeline, the second area is processed at the second pipeline, and the third and the fourth areas are processed at the third and the fourth pipelines respectively. Each pipeline processes by the patch. Reading data from the area RAM and writing the result of the process (an access cycle in the figure) and mixing operation of input data and RAM data (a multiplication cycle) are carried out concurrently. The mixing operation during the drawing processing is accelerated by providing a plurality of drawing pipelines; however, the number of times for access to the area RAM
10
is not decreased. For example, if a patch comprises 10K pixels and if processing for 10 patches is necessary, the number of times for access to the area RAM
10
will be once each for reading and writing. Since access to each pixel is executed twice per patch, the total will be 200K, that is 10K×10K×2. Thus, there is a limit with concurrent processing, while the operation can be accelerated, since the number of times for access to a memory is not decreased. In a word, it is necessary not only to accelerate the operation during the drawing processing, but also to accelerate the access to the memory.
SUMMARY OF THE INVENTION
The object of the invention is to decrease the number of times for access to a memory, and to simplify acceleration of drawing input processing. The image creation apparatus according to the invention stores an image being created in a memory, displays the image on a monitor, receives drawing input data by a patch comprising a plurality of pixels in response to specification of a position on the displayed image. It is characterized by:
a drawing pipeline including means for specifying a processing area comprising at least a pixel selected from a drawing area comprising a plurality of patches, and means for processing said processing area for said plurality of patches. According to the invention, it is not that a drawing area is processed by the patch, or the next patch is processed after processing for a patch is completed. It is rather that a plurality of patches are processed by the processing area comprising a few numbers of pixels, and the next processing area is processed after the above processing area is processed.
Preferably, a plurality of said drawing pipelines are provided, said processing area is divided spatially, allocated to, and processed concurrently by each drawing pipeline.
Preferably, said processing means includes a density data generator which generates drawing density data for a pixel by each patch placed in series, a multiplier, and a register, and said multiplier repeats the multiplication of the stored data of a register and the data of said density data generator for a plurality of patches.
Further preferably, said processing area comprises a pixel, said register comprises an accumulator, and the structure of a drawing pipeline is simplified. And one same pixel is processed for a number of patches repeatedly.
Preferably, a cache memory is connected to the output of said drawing pipeline and is utilized as a buffer between memory which stores an image and a drawing pipeline. The cache may be a small-size cache which can not store the whole allocated area.
According to the invention, there is provided an image creation method storing an image being created in a memory, displaying the image on a monitor, specifying a position in the displayed image, and receiving drawing data input by a patch, characterized by:
dividing a drawing area comprising a plurality of patches into a plurality of groups each comprising a plurality of pixels;
allocating said plurality of groups to a plurality of drawing pipelines;
determining a processing area in each of said plurality of groups comprising at least a pixel for each drawing pipeline;
processing said plurality of patches for the determined processing area; and
repeating the steps of said determining the processing area and said processing said plurality of patches, until each of said plurality of groups is processed.
According to the invention, the processing for a next processing area is started after the processing for a former processing area which extends a plurality of patches but comprises at least a pixel is finished. For that reason, the number of times for access to the memory for each pixel in a drawing area is once for each reading and writing. The number of patches increases, but the number of times for access to the memory does not increase so much. As a result, the invention reduces the number of times for access to the memory, and drawing input is accelerated in terms of access according to the invention. To accelerate the drawing processing, preferably a plurality of drawing pipelines are provided, and a drawing area is divided spatially and allocated to said plurality of drawing pipelines. The operation speed improves through concurrent processing, and the number of times for access to the memory is controlled not to increase since the processing is carried out by the processing area not by the patch. The drawing processing
Arent Fox Kintner & Plotkin & Kahn, PLLC.
Chauhan Ulka J.
Shima Seiki Manufacturing Ltd.
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