Computer graphics processing and selective visual display system – Computer graphics processing – Attributes
Reexamination Certificate
1999-12-01
2002-02-19
Brier, Jeffery (Department: 2672)
Computer graphics processing and selective visual display system
Computer graphics processing
Attributes
C345S547000, C348S581000, C348S448000, C348S715000, C382S260000, C382S265000, C382S276000
Reexamination Certificate
active
06348926
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image conversion method and an image conversion apparatus for allowing a matrix type fix display device, such as a liquid crystal display, to display image signals of various types of systems.
2. Description of the Background Art
Among methods which are used to display image signals of various types of systems in a matrix type fix display device are, as introduced in “Image Analysis Handbook (University of Tokyo Press),” nearest neighbor interpolation, bi-linear interpolation, cubic convolution interpolation and the like. Means for embodying such methods may be a method externally using a memory which can be accessed at random as described in U.S. Pat. No. 4,631,450, for example.
FIG. 6
is a block diagram of a conventional image conversion apparatus. In
FIG. 6
, frame memories
401
,
403
are accessible at random and have a function of converting horizontal scanning and vertical scanning of one frame of sampled image signals and outputting the signals. A vertical conversion filter
402
executes processing for expanding or reducing an image in the vertical direction. A horizontal conversion filter
404
executes processing for expanding or reducing an image in the horizontal direction. An address generator
405
generates horizontal addresses and vertical addresses which are to be supplied to the frame memory
401
as well as to the vertical conversion filter
402
. An address generator
406
generates horizontal addresses and vertical addresses which are to be supplied to the frame memory
403
as well as to the horizontal conversion filter
404
.
Next, operations of the image conversion apparatus will be described. In the image conversion apparatus, first, input image signals are written in the frame memory
401
in the order of horizontal scanning of the input signals, in accordance with outputs from the address generator
405
, namely, write addresses. The frame memory
401
reads in the order of vertical scanning, in accordance with outputs from the address generator
405
, namely, read addresses, for the purpose of conversion of horizontal scanning into vertical scanning.
The signals thus read out are supplied to the vertical conversion filter
402
which thereafter expands or reduces the signals in the vertical direction. At this stage, as the address generator
405
supplies addresses to the vertical conversion filter
402
, depending on the contents of these addresses, read addresses in the frame memory
401
may be changed to thereby accordingly control (change) a filtering characteristic of the vertical conversion filter
402
. That is, as the addresses are supplied, it is possible to change the filtering characteristic (filtering contents) in accordance with vertical positions.
Next, outputs from the vertical conversion filter
402
are written in the frame memory
403
in the order of the outputs in accordance with outputs from the address generator
406
, namely, write addresses. For conversion of vertical scanning into horizontal scanning, the frame memory
403
reads in the order of horizontal scanning in accordance with outputs from the address generator
406
, namely, read addresses.
Image signals outputted from the frame memory
403
are in the horizontal and vertical scanning condition of the input image signals which were supplied to the frame memory
401
.
The signals read from the frame memory
403
are thereafter supplied to the horizontal conversion filter
404
which then expands or reduces the images in the horizontal direction. At this stage, as the address generator
406
supplies addresses to the horizontal conversion filter
404
, depending on the contents of these addresses, read addresses in the frame memory
403
may be changed to thereby accordingly control (change) a filtering characteristic of the horizontal conversion filter
404
. That is, as the addresses are supplied, it is possible to change the filtering characteristic (filtering contents) in accordance with horizontal positions.
However, in a structure according to the conventional technique as described above, where one wishes to use filtering means of a multi-tap structure for handling a large quantity of pixel data which are needed for processing, it is necessary to execute a memory access for reading the pixel data from a frame memory at a speed which is defined as a cycle speed of the pixel data multiplied by the number of the taps of the filtering means.
As herein termed, filtering refers to interpolation in pixel conversion processing. However, in a broad sense, filtering also means bandwidth restriction processing, aperture processing, etc.
For example, where input image signals is XGA signals (1,024 dots in the horizontal direction×768 dots in the vertical direction) of 60 Hz and 4-tap filtering means is to be used, since a cycle speed of pixel data is 65 MHz, it is necessary to read out pixel data while accessing a frame memory at 260 MHz.
Accessing a memory at such a high speed is very difficult considering the specifications of currently available memories, and hence, can not be realized without a difficulty.
SUMMARY OF THE INVENTION
The present invention aims at providing an image conversion method, an image conversion apparatus and a liquid crystal projector for realizing image conversion utilizing filtering processing with a multi-tap structure without requiring a memory to use a high-speed capability.
A first aspect of the present invention is directed to an image conversion method in which output image signals are generated through filtering processing which uses a plurality pieces of continuous pixel data of input image signals which are sampled, wherein pixel data of approximately one frame of said input image signals are stored in first memory means, a larger quantity of continuous pixel data containing a plurality pieces of continuous pixel data needed for said filtering processing are read in advance from said first memory means and stored in second memory means, the plurality pieces of continuous pixel data needed for said filtering processing are selected from said second memory means, and said output image signals are generated through said filtering processing which uses the selected plurality pieces of pixel data.
According to the method described above, it is possible to output a plurality pieces of continuous pixel data from the first memory means for one access and select necessary pixel data from the second memory means, and therefore, it is possible to realize image conversion which does not require high-speed memory accessing.
A third aspect of the present invention is directed to an image conversion apparatus which generates output image signals through filtering processing which uses a plurality pieces of continuous pixel data of input image signals which are sampled, comprising: filtering means which generates said output image signals from said plurality pieces of continuous pixel data; merging means which receives said input image signals, and merges and outputs said input image signals for every plurality pieces of continuous pixel data; first memory means which receives an output from said merging means and stores pixel data of approximately one frame; second memory means which receives an output from said first memory means, and stores and outputs a larger quantity of continuous pixel data than a plurality pieces of continuous pixel data required by said filtering means; selecting means which receives an output from said second memory means, and selects and outputs the plurality pieces of continuous pixel data required by said filtering means; and third memory means which stores and outputs address data which are calculated in advance to control an output from said first memory means and control data which are calculated in advance to control a filter factor of said filtering means, wherein said filtering means receives an output from said selecting means, and in accordance with the address data in said third memory means, said first memory outp
Hirotsune Satoshi
Muraji Tsutomu
Nozawa Kazushi
Brier Jeffery
Sajous Wesner
Stevens Davis Miller & Mosher LLP
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