Image coding/decoding apparatus for efficient processing by shar

Television – Bandwidth reduction system – Data rate reduction

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

348384, 348390, 348403, 348409, H04N 750

Patent

active

054915155

ABSTRACT:
An image coding/decoding apparatus intended for efficient processing by sharing members in coding, local decoding, and decoding processing. Processes such as DCT and IDCT, zigzag scan conversion and inversion, or quantization and inverse quantization performed in coding, local decoding, and decoding processing are similar to each other. DCT/IDCT, zigzag scan conversion/inversion, and quantization/inverse quantization are provided where either of the two functions can be selected for execution in synchronization with the processing timing for each block. Since the time required for one process for data for each block is very short, overall processing is not affected even if the members are used in a time division manner. By sharing processing, the hardware scale can be made small and by using a data bus in a time division manner, an external data bus can also be eliminated.

REFERENCES:
patent: 4707738 (1987-11-01), Ferre
patent: 4809067 (1989-02-01), Kikuchi
patent: 5130797 (1992-07-01), Murakami et al.
patent: 5164980 (1992-11-01), Bush et al.
patent: 5202760 (1993-04-01), Tourtier et al.
patent: 5253078 (1993-10-01), Balkanski et al.
Artieri, et al "A Chip Set Core for Image Compression" 1990 IEEE SGS-Thomson Microelectronics.
Technology Update, Video-Compression Chips "Monolithic Circuits Expedite Desktop Video" Electrical Design News Oct. 24, 1991.
1991 Symposium on VLSI Circuits Diget of Technical Papers May 30, 1991 Circuits Symposium.
IC Executes Still-Picture Compression Algorithms--Electronic Design May 23, 1991.
Proceedings of the IEEE 1991 Custom Integrated Circuits Conferenc May 12, 1991.
Purcell "The C-Cuibe CL550 JPEG Image Compression Processor" Comp-Con 91 Digest Of Papers.
Tamitani, et al "An Encoder/Decoder Chip Set for the MPEG Video Standard" ICASSP-92 D2EV Digital Signal Processing 2 Estimation.
InfoChip Systems Incorporated, Preliminary Information IC801 "Single Chip Px64 Codec For Video Phones".
"100 Mbit/s HDTV Transmission Using a High Efficienty Codec" by Y. Yashima & K. Sawada Signal Processing of HDTV II, 1990, pp. 579-586.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Image coding/decoding apparatus for efficient processing by shar does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Image coding/decoding apparatus for efficient processing by shar, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Image coding/decoding apparatus for efficient processing by shar will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-243396

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.