Image clock signal generating system with initial phase matching

Details Image clock signal generating system with initial phase matching Image clock signal generating system with initial phase matching

1989-10-13

1992-06-16

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307511, 307359, 328 63, 328 72, 328155, H03K 513, H03K 700, H03K 5153, H03K 700

Patent

active

051226782

ABSTRACT:
An image clock signal generating system generates an image clock signal which is used to enable and disable a scan of an optical scanner, and comprises a phase locked loop (PLL) circuit for generating an image clock signal in response to a reference pulse signal which comprises a plurality of pulses during a time corresponding to a scan range of the optical scanner and no pulses during a time corresponding to a no-scan range of the optical scanner. The PLL circuit includes a phase comparator which receives the reference pulse signal and a feedback signal and outputs a phase error signal dependent on a phase error between the two signals, a voltage controlled oscillator (VCO) for outputting an image clock signal, and an initial phase matching circuit for outputting the feedback signal in response to the image clock signal output from the VCO. The initial phase matching circuit outputs the feedback signal with an initial phase which makes the phase error between the reference pulse signal and the feedback signal approximately the same as a predetermined phase error detected in the phase comparator when the PLL circuit is in a locked state.

REFERENCES:
patent: 3781470 (1973-12-01), Horn
patent: 4975650 (1990-12-01), Martin
"Transistor Technology", Analog IC Application Handbook, CQ Publishing K.K., Jan. 1, 1987, pp. 199-200.

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