Illegal address detector for semiconductor memories

Details Illegal address detector for semiconductor memories Illegal address detector for semiconductor memories

1992-01-24

1994-02-15

Fears, Terrell W.

Static information storage and retrieval

Addressing

36518907, 365207, G11C 1300

Patent

active

052873218

ABSTRACT:
When a user requests a RAM or other semiconductor memory to be compiled with a number of rows that is not a power of two, the compiler creates the RAM with one extra row. The rows requested by the user are placed at contiguous row addresses starting at zero and ending at one less than the number of rows requested. The highest of these row addresses is placed permanently in a comparator by the compiler. The comparator then compares each row address input to the RAM to the row address contained in the comparator. If the row address input is higher, then the comparator selects the extra row. The extra row can be written into or read from in the same manner as any other row in the RAM. The delay of the comparator is comparable to the delay of the address decoder, so that the RAM operates within the same specifications regardless of whether the address decoder selects a row or the comparator selects the extra row.

REFERENCES:
patent: 4675808 (1987-06-01), Grinn et al.
patent: 5121354 (1992-06-01), Mandalia

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