ILD planarization method

Details ILD planarization method ILD planarization method

2000-11-29

2002-08-13

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S694000

Reexamination Certificate

active

06432827

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a dynamic random access memory(DRAM), and more particularly, to a method of planarization for an inter layer dielectric (ILD) in the process of manufacturing a dynamic random access memory.
2. Description of the Prior Art
Dynamic random access memory (DRAM) devices are used extensively in the electronics industry for information storage. A high density DRAM, such as a
64
megabit DRAM, is comprised of millions of memory cells. Each memory cell on the DRAM chip is comprised of a pass transistor, e.g. a metal-oxide-semiconductor field-effect transistor (MOSFET), and a storage capacitor for storing charge. An embedded DRAM (EDRAM) is a type of integrated circuit (IC) that combines both DRAM circuits and logic circuits in a semiconductor substrate. Nowadays, the trend in manufacturing semiconductor ICs is the integration of memory cell arrays with high-speed logic circuit elements. For example, microprocessors or digital signal processors all have integrated circuits that incorporate embedded memory.
However, the prior method of fabricating an EDRAM encounters a serious topographical problem of an ILD layer before the implementation of a metallization process. More specifically, the problem of the prior method results from a large height difference on the ILD layer between a memory array area and a periphery circuit region in an EDRAM. The problem of height difference is a critical factor in determining the production yield.
The steps involved in manufacturing a conventional EDRAM on a semiconductor wafer
50
are illustrated in
FIG. 1
to FIG.
8
. Referring to
FIG. 1
, the semiconductor wafer
50
is comprised of a silicon substrate
52
on which a memory array area
10
and a periphery circuit region
12
are previously defined. The memory array area
10
is comprised of capacitors
18
a
,
18
b
and gates
14
, while the periphery circuit region
12
is comprised of a plurality of gates
15
on the silicon substrate
52
. In the memory array area
10
, the capacitors
18
a
,
18
b
are formed on an atmospheric-pressure chemical vapor deposition (CVD) oxide (AP oxide) layer
22
of an approximately even surface. The gates
14
,
15
are covered by a phosphosilicate glass (PSG) layer
20
. A plug
16
formed in the AP oxide layer
22
and the PSG layer
20
functions to electrically connect the capacitors
18
a
and the underlying source or drain (not explicitly shown) within the silicon substrate
52
.
In
FIG. 1
, a borophosphosilicate glass (BPSG) layer
24
acting as a buffer layer, covering both the memory array area
10
and the periphery circuit region
12
, is first formed on the surface of the semiconductor wafer
50
. A difference in height on the BPSG layer
24
is created between the memory array area
10
and the periphery circuit region
12
due to the presence of the capacitors
18
a
,
18
b
. The large height difference (step height), which ranges from 6000 to 9000 angstroms, can lead to a more complicated fabrication process due to difficulties in the formation of a contact window/plug in a subsequent fabrication process.
Referring to
FIG. 2
, a conventional anisotropic dry etching process is performed to etch the BPSG layer
24
down to the surface of the AP oxide layer
22
to form a spacer
26
along the edge of the memory array area
10
. The spacer
26
functions to release the surface stress from the semiconductor wafer
50
that occurs in subsequent processes. Then, a PSG layer
32
with a thickness of approximately 3000 to 7000 angstroms is deposited on the surface of the semiconductor wafer
50
. Thereafter, a thermal re-flow process is performed between the memory array area
10
and the periphery circuit region
12
to reduce the step height to approximately 4000 to 8000 angstroms.
Referring now to
FIG. 3
, using a conventional lithographic method, a patterned and developed photoresist layer
42
is formed on the semiconductor wafer
50
to expose only the memory array area
10
in the BPSG layer
32
. An etch back process is subsequently performed to etch away a predetermined thickness from the BPSG layer uncovered by the photoresist layer
42
. The result is a BPSG layer
32
with a thickness of approximately 1000 angstroms covering the memory array area
10
. Next, as shown in
FIG. 4
, a photoresist ashing process and a series of cleaning procedures are carefully performed to remove the photoresist layer
42
to obtain a clean semiconductor wafer surface.
In
FIG. 5
, a conventional chemical mechanical polishing (CMP) process is performed to planarize the BPSG layer
32
. Extreme caution must be taken during the CMP process to prevent breakthrough of the BPSG layer
32
over the capacitors
18
a
,
18
b
. To form a more uniform surface, as shown in
FIG. 6
, a conventional chemical vapor deposition (CVD) technique is performed to deposit a PSG layer
44
, with an approximate thickness of 1000 angstroms, over the BPSG layer
32
.
In
FIG. 7
, by means of both a conventional lithographic technique and a dry etching process, a contact plug
46
is formed in the periphery circuit region
12
. The contact plug
46
spans the PSG layer
44
, the AP oxide layer
22
and the PSG layer
20
through to the surface of the silicon substrate
52
. The contact plug
46
functions to electrically couple a subsequently formed upper layer metal to the underlying devices on the silicon substrate
52
. Finally, as shown in
FIG. 8
, a metal layer
48
is formed atop the PSG layer
44
to thereby complete the fabrication of a conventional EDRAM.
As indicated above, the prior method of fabricating an EDRAM has the following drawbacks: (1) the spacer
26
is required to release stress in the prior art process; (2) an additional BPSG layer
24
and an etching process are therefore needed to form the spacer
26
; (3) an additional thick PSG layer
32
is required; (4) an additional thermal re-flow process is required to obtain a smoother PSG layer
32
; (5) an additional lithographic process and an etching process are needed to remove a predetermined thickness from the PSG layer
32
over the memory array area
10
; and (6) a costly CMP process is also needed. Consequently, the prior art method of fabricating an EDRAM is inefficient, time-consuming and costly.
The method of manufacturing an EDRAM according to the prior art is inefficient and time-consuming and the present invention can improve upon these drawbacks(5).
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an efficient and time-saving method for manufacturing an EDRAM. It is another object to provide a method for manufacturing an EDRAM to solve the above-mentioned problem of step height difference between the memory array area and the periphery circuit region.
In accordance with the claimed invention, the method comprises providing a semiconductor wafer having both a memory array area and a periphery circuit region defined on its surface, a plurality of metal oxide semiconductor (MOS) transistors installed in the periphery circuit region, and a plurality of metal oxide semiconductor (MOS) transistors and capacitors formed by a top electrode. Then, a dielectric layer and a storage node are installed in the memory array area. Next, a dielectric layer is formed on the surface of the semiconductor wafer covered by the metal oxide semiconductor(MOS) transistors and capacitors followed by the formation of a photoresist layer on the surface of the dielectric layer. Thereafter, a photolithographic process is performed to removeportions of the photoresist layer above the memory array area. The residual photoresist layer functions as a hard mask to etch the dielectric layer in the memory array area by a predetermined depth exceeding 6000 angstroms. Finally, a CMP process is performed to planarize the dielectric layer of the EDRAM.
It is an advantage of the present invention that a photolithographic process is performed through the use of layout patterns of either the

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