III-V on Si heterostructure using a thermal strain layer

Details III-V on Si heterostructure using a thermal strain layer III-V on Si heterostructure using a thermal strain layer

1989-03-02

1990-02-13

Hearn, Brian E.

Metal treatment

Barrier layer stock material, p-n type

With contiguous layers of different semiconductive material

148 335, 148DIG25, 148DIG97, 156610, 437126, 437132, 437247, 437976, H01L 2912, H01L 2906

Patent

active

049003720

ABSTRACT:
A method for producing wafers having deposited layers of III-V materials on Si or Ge/Si substrates is disclosed. The method involves the use of multiple in situ and ex situ annealing steps and the formation of a thermal strain layer to produce wafers having a decreased incidence of defects and a balanced thermal strain. The wafers produced thereby are also disclosed.

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