Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
1994-08-15
2001-04-17
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S012000, C257S014000, C257S025000
Reexamination Certificate
active
06218677
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to electronic devices, and, more particularly, to resonant tunneling devices and systems.
The continual demand for enhanced transistor and integrated circuit performance has resulted in improvements in existing devices, such as silicon bipolar and CMOS transistors and gallium arsenide MESFETs, and also in the introduction of new device types and materials. In particular, scaling down device sizes to enhance high frequency performance leads to observable quantum mechanical effects such as carrier tunneling through potential barriers. This led to development of alternative device structures such as resonant tunneling diodes and resonant tunneling hot electron transistors which take advantage of such tunneling phenomena.
Resonant tunneling diodes are two terminal devices with conduction carriers tunneling through potential barriers to yield current-voltage curves with portions exhibiting negative differential resistance. Recall that the original Esaki diode had interband tunneling (e.g., from conduction band to valence band) in a heavily doped PN junction diode. An alternative resonant tunneling diode structure relies on resonant tunneling through a quantum well in a single band; see
FIG. 1
which illustrates a AlGaAs/GaAs quantum well. Further, Mars et al., Reproducible Growth and Application of AlAs/GaAs Double Barrier Resonant Tunneling Diodes, 11 J.Vac.Sci.Tech.B 965 (1993), and Özbay et al, 110-GHz Monolithic Resonant-Tunneling-Diode Trigger Circuit, 12 IEEE Elec.Dev.Lett. 480 (1991), each use two AlAs tunneling barriers imbedded in a GaAs structure to form a quantum well resonant tunneling diode. The quantum well may be 4.5 nm thick with 1.7 nm thick tunneling barriers.
FIG. 2
illustrates current-voltage behavior at room temperature. Note that such resonant tunneling “diodes” are symmetrical. With the bias shown in
FIG. 3
a,
a discrete electron level (bottom edge of a subband) in the quantum well aligns with the cathode conduction band edge, so electron tunneling readily occurs and the current is large. Contrarily, with the bias shown in
FIG. 3
b
the cathode conduction band aligns between quantum well levels and suppresses tunneling, and the current is small.
Attempts to fabricate quantum wells in silicon-based semiconductors, rather than the III-V semiconductors such as AlGaAs and GaAs, have focussed primarily on silicon-germanium alloys. For example, the Topical Conference on Silicon-Based Heterostructures II (Chicago 1992) included papers such as Grützmacher et al., Very Narrow SiGe/Si Quantum Wells Deposited by Low-Temperature Atmospheric Pressure Chemical Vapor Deposition, 11 J.Vac.Sci.Tech.B 1083 (1993)(1 nm wide wells of Si
0.75
Ge
0.25
with 10 nm wide Si tunneling barriers) and Sedgwick et al., Selective SiGe and Heavily As Doped Si Deposited at Low Temperature by Atmospheric Pressure Chemical Vapor Deposition, 11 J.Vac.Sci.Tech.B 1124 (1993)(Si/SiGe resonant tunneling diode selectively grown in an oxide window with silicon tunneling barriers each 5 nm wide and a 6 nm wide quantum well of Si
0.75
Ge
0.25
. Because the valence band offset greatly exceeds the conduction band offset at SiGe/Si interfaces, most investigators consider hole tunneling rather than electron tunneling using strained layer SiGe.
However, SiGe strained layers possess a serious intrinsic impediment in that the band discontinuities are small (less than 500 meV). This precludes room temperature operation with large peak-to-valley curent differences (greater than approximately 5). Further, the addition of a strained heterojunction and new material, germanium, necessitates the undesirable development and implementation of new low temperature fabrication methods to allow production.
Another epitaxial approach for silicon-based quantum wells uses calcium fluoride (CaF
2
) as the tunneling barriers. Calcium fluoride lattice matches silicon for (111) oriented interfaces and may be epitaxially grown by molecular beam epitaxy. See Schowalter and Fathauer, 15 CRC Crit. Rev. Solid State Mater. Sci. 367 (1989); Cho et al., 10 J.Vac. Sci. Tech. A 769 (1992); and Cho et al., U.S. Pat. Nos. 5,229,332 and 5,229,333.
Tsu, U.S. Pat. No. 5,216,262, describes a silicon-based quantum well structure with tunneling barriers made of short period silicon/silicon dioxide superlattices of epitaxial silicon dioxide two monolayers thick.
Numerous investigators have studied the silicon/silicon oxide interface because it underlies performance of the currently prevalent CMOS transistor structure of silicon integrated circuits. The growth and analysis of single molecular layers of oxide have become commonplace. For example, Ohmi et al., Very Thin Oxide Film on a Silicon Surface by Ultraclean Oxidation, 60 Appl.Phys.Lett. 2126 (1992); Hattori, High Resolution X-ray Photoemission Spectroscopy Studies of Thin SiO
2
and Si/SiO
2
Interfaces, 11 J.Vac.Sci.Tech.B 1528 (1993); and Seiple et al., Elevated Temperature Oxidation and Etching of the Si(111) 7×7 Surface Observed with Scanning Tunneling Microscopy, 11 J.Vac.Sci.Tech.A 1649 (1993). The Ohmi et al. article observes that an oxide monolayer formed on a silicon wafer at 300° C. provides the foundation for oxide films superior to standard thermal oxide with respect to Frenkel-Poole emission for thin oxide films.
SUMMARY OF THE INVENTION
The present invention provides resonant tunneling with nitride-based III-V compounds lattice matched to silicon. The nitride-based III-V compounds may also be lattice matched to other substrate such as gallium phosphide.
This has technical advantages including fabrication of resonant tunneling devices with standard silicon-compatible processes and thus integration with other silicon devices such as CMOS and bipolar transistors.
REFERENCES:
patent: 5583351 (1996-12-01), Brown et al.
patent: 0 385 392 (1990-10-01), None
patent: 0 487 823 (1992-06-01), None
Baumeister Bradley William
Brady W. James
Hoel Carlton H.
Saadat Mahshid
Telecky , Jr. Frederick J.
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