III-V group compound semiconductor device including a buffer...

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor

Reexamination Certificate

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C257S183000, C257S194000, C257S615000, C257SE29246, C257SE21371, C257SE21387, C257SE21403, C257SE21407

Reexamination Certificate

active

07902571

ABSTRACT:
A field effect transistor (FET) with high withstand voltage and high performance is realized by designing a buffer layer structure appropriately to reduce a leakage current to 1×10−9A or less when a low voltage is applied. An epitaxial wafer for a field effect transistor comprising a buffer layer2, an active layer, and a contact layer on a semi-insulating substrate1from the bottom, and the buffer layer2includes a plurality of layers, and a p-type buffer layer composed of p-type AlxGa1-xAs (0.3≦x≦1) is provided as a bottom layer (undermost layer)2a. A Nd product of a film thickness of the p-type buffer layer and a p-type carrier concentration of the p-type buffer layer is within a range from 1×1010to 1×1012/cm2.

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Ohno et al., “Suppression of GDS frequency dispersion in heterojunction FETs with a partially depleted p-type buffer layer”, Solid-State Electronics 43 (1999) pp. 1339-1345.

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