Active solid-state devices (e.g. – transistors – solid-state diode – Incoherent light emitter structure – With heterojunction
Reexamination Certificate
2001-05-29
2003-10-07
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Incoherent light emitter structure
With heterojunction
C257S101000, C257S102000, C257S103000
Reexamination Certificate
active
06630692
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor light emitting devices and more particularly to III-Nitride light emitting devices.
BACKGROUND
III-Nitride semiconductors are an important class of III-V compound semiconductors. III-Nitride light emitting devices are based on semiconducting alloys of nitrogen with elements from group III of the periodic table. Examples of such III-Nitride devices include In
x
Al
y
Ga
1-x-y
N (0≦x≦1,0≦y≦1,x+y≦1) based light emitting diodes (LEDs) and laser diodes (LDs). Such III-Nitride light emitting devices are commercially valuable high brightness sources of, for example, ultraviolet, blue, and green light.
The wall plug efficiency of a light emitting device is the ratio of optical power coupled out of the device to the electrical power supplied to the device. A high wall plug efficiency is generally advantageous. The wall plug efficiency of an LED or LD is inversely proportional to the driving (forward) voltage V
f
that must be applied to the device for it to emit light when driven at the desired current I
f
. The theoretical lower limit for V
f
is determined by the energy of the photons emitted by the device. Unfortunately, the driving voltage of conventional III-Nitride light emitting devices is typically much higher than this lower limit.
The high driving voltage of conventional III-Nitride light emitting devices results in part from high series resistance in the n-type III-Nitride device layers. Potential energy barriers (n-contact barriers) at the interface of n-type semiconductor device layers with (typically metal) electrical contacts also contribute to these high driving voltages.
The series resistance in n-type III-Nitride layers and n-contact barriers associated with those layers can be reduced by increasing the doping density of electron donor impurities, typically Si atoms, in the III-Nitride layer. For planar devices, the series resistance can also be decreased by increasing the thickness of the n-type III-Nitride layers. However, incorporation of Si atoms into a III-Nitride layer generates in-plane tensile strain in the layer. At a sufficiently high Si doping density, the tensile strain cracks the III-Nitride layer and may thus render it unusable as a light emitting device. The Si doping density at which cracking of a III-Nitride layer occurs decreases as the layer is made thicker.
FIG. 1A
illustrates relationships between Si doping density, III-Nitride layer thickness, and cracking. Combinations of Si doping concentration and layer thickness form regions where transitions from uncracked to cracked layers occur. Line
1
indicates combinations of Si doping density and GaN layer thickness at a transition between cracked and uncracked GaN layers prepared by a conventional “two-step” growth process in which the GaN layer is grown directly on a low-temperature nucleation layer by metal-organic chemical vapor deposition (MOCVD). GaN layers prepared by this conventional process and having silicon doping and thickness combinations above line
1
typically crack. For example, for a 1 micron (&mgr;m) thick GaN layer, the Si doping concentration is limited by cracking to below 1×10
19
per centimeter cubed (cm
−3
) for a GaN layer prepared by the conventional two-step method. Either increasing the Si doping concentration or increasing the thickness of the layer will cause the layer to crack.
Such doping/thickness limitations are typically observed for conventional two-step growth of Si doped GaN layers by the inventors and others. (Data point 3 is from Murakami et al., J. Crystal Growth 115 (1991) 648-651.) However, the formation of uncracked, 4 &mgr;m thick GaN layers with a Si doping concentration of ~2×10
19
cm
−3
directly on a low-temperature nucleation layer has been reported by S. Nakamura et al., Japanese Journal of Applied Physics 31,2883-2888 (1992). Nakamura et al. concluded that their use of an unconventional two-flow MOCVD reactor enabled them to produce the crack-free GaN layers with high Si concentration. In this two-flow reactor an additional vertical subflow of inert gas is combined with a horizontally injected source gases. Such unconventional reactors are not generally available.
The high driving voltages of conventional III-Nitride light emitting devices also result, in part, from the piezoelectric nature of the III-Nitride crystal structures. The active regions of III-Nitride light emitting devices typically include one or more quantum well layers and one or more barrier layers. These layers typically have compositions that differ from each other and differ from the surrounding layers in the device. Consequently, these layers are typically strained. As a result of this strain and of the piezoelectric nature of the III-Nitride crystal structure, the regions near the interfaces of quantum well layers and barrier layers in the active regions of III-Nitride light emitting devices experience piezoelectric fields. These piezoelectric fields, combined with heterojunction band offsets, produce interface energy barriers that impede the transport of electrons and holes into the active region and increase the driving voltage of the light emitting device.
What is needed is a III-Nitride light emitting device that overcomes the above drawbacks of conventional III-Nitride devices.
SUMMARY
Light emitting devices having improved performance are provided. In one embodiment, a light emitting device includes a substrate, a nucleation layer disposed on the substrate, a defect reduction structure disposed above the nucleation layer, and an n-type III-Nitride semiconductor layer disposed above the defect reduction structure. The n-type layer has, for example, a thickness greater than or equal to about one micron and a silicon dopant concentration greater than or equal to about 10
19
cm
−3
.
In one implementation the defect reduction structure includes a defect reduction layer. The defect reduction layer may reduce the defect density in the n-type layer to about 2×10
9
cm
−2
or less and increase compressive strain in the n-type III-Nitride semiconductor layer so that the a-lattice parameter is less than 3.187 Angstroms (Å). The defect reduction layer may be formed, for example, from source gases including NH
3
, trimethylgallium, and H
2
with the ratio of the partial pressure of NH
3
to the partial pressure of trimethylgallium about 200 to about 1500 and the ratio of the partial pressure of NH
3
to the partial pressure of H
2
about 0.05 to about 0.35.
In another implementation the defect reduction structure includes a III-Nitride semiconductor layer on which is disposed a silicon containing material. In another implementation the defect reduction structure includes one or more nucleation layers. In another implementation a growth surface of the defect reduction structure is roughened prior to growth of the n-type layer. Such a rough growth surface may be produced, for example, by interrupting growth of a III-Nitride layer and exposing it to an etching environment for about 1 to about 1000 seconds.
In some implementations, barrier layers in the active region of the light emitting device are doped with acceptor and/or donor impurities. The concentration profiles of the impurities may be either spatially uniform or spatially non-uniform.
In another embodiment, a light emitting device includes an active region that includes at least one barrier layer either uniformly doped with an impurity or doped with an impurity having a concentration graded in a direction substantially perpendicular to the active region. The concentration of the impurity may be graded to at least partially cancel an effect of a piezoelectric field in the active region.
Light emitting devices in accordance with embodiments of the present invention may exhibit advantageously low series resistance, n-contact barrier, and driving voltage. Advantageously, light emitting devices in accordance with embodiments of the present invention may be fabricated, for example, in conventiona
Gardner Nathan Fredrick
Goetz Werner
Kern Richard Scott
Kim Andrew Youngkyu
Kocot Christopher P.
Flynn Nathan J.
Forde Remmon R.
Lumileds Lighting U.S. LLC
Patent Law Group LLP
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