Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
2002-04-03
2003-05-06
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S198000, C257S200000, C257S201000, C438S235000, C438S309000, C438S312000
Reexamination Certificate
active
06559482
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90133089, filed Dec. 31, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a III-N compound semiconductor device structure and method of manufacture. More particularly, the present invention relates to a III-N compound semiconductor heterojunction bipolar transistor (HBT) structure and method of manufacture.
2. Description of Related Art
Recent progress in semiconductor fabrication technologies has lead to the development of gallium nitride-based semiconductor devices such as gallium nitride (GaN), gallium aluminum nitride (GaAlN), and gallium indium nitride (GaInN) transistors.
FIG. 1
is a schematic structural diagram of a conventional III-N compound semiconductor heterojunction bipolar transistor (HBT) structure.
As shown in
FIG. 1
, the heterojunction bipolar transistor is formed over a substrate
100
such as an aluminum oxide (Al
2
O
3
) substrate. A nucleation layer
102
and an intrinsic buffer layer
104
are formed in sequence over the substrate
100
. The intrinsic buffer layer
104
can be undoped gallium nitride (GaN) layers, for example. A heavily N-doped gallium nitride (n
+
—GaN) layer
106
is formed over the intrinsic buffer layer
104
serving as a collector contact layer in the HBT structure. A lightly N-doped gallium nitride (N
−
—GaN) layer
108
and a P-doped gallium nitride layer
110
are formed in sequence over the intrinsic buffer layer
104
. The P-doped gallium nitride layer
110
serves as a base in the HBT structure. A heavily N-doped aluminum gallium nitride (n
+
—Al
x
Ga
1−x
N) layer
112
and a heavily N-doped gallium nitride (n
30
—GaN) layer
114
are formed in sequence over the P-doped gallium nitride layer
110
. The heavily N-doped gallium nitride (n
+
—GaN) layer
114
serves as an emitter contact layer in the HBT structure.
In the aforementioned HBT structure, each epitaxial layer is formed in sequence. To form various electrodes, a reactive ion etching (RIE) must be conducted to remove a portion of the epitaxial layer from the surface of the lower few layers so that the surface of those layers are exposed. Metallic contacts are formed over the exposed surface to serve as electrode terminals such as a base electrode B and a collector electrode C. However, after an RIE treatment of the P-doped gallium nitride layer
110
(that serves as a base for the HBT structure), a good ohmic contact between the metallic electrode B and the gallium nitride material layer
110
is hard to form.
In general, the activation energy of dopants in P-doped gallium nitride-based compound is low and the energy gap of the gallium nitride compound is wider than the conventional semiconductor material. Hence, high concentration of P-type carriers (hole) is difficult to obtain. In addition, because magnesium (Mg) and hydrogen (H) ions may combine to form Mg—H compound when P-type dopants are incorporated into a gallium nitride material layer, magnesium (Mg) is difficult to dissociate back into ions and release a hole carrier. Moreover, most RIE processes will damage the surface of a P-doped gallium nitride layer and produce nitrogen vacancies. These nitrogen vacancies are thought to be negatively charged defects that may combine with the holes in a P-type material and serve as a compensatory mechanism to reduce the total number of holes. In other words, hole concentration near the surface of P-type gallium nitride material layer is reduced after a RIE process. Ultimately, a good ohmic contact with a metallic layer is difficult to form.
In addition, the conventional method uses an etching process to expose the base and the collector region in a gallium nitride material layer in preparation for forming the base electrode B and the collector electrode C after the growth of epitaxial layers. Therefore, device surfaces are highly non-planar leading to greater difficulties in device integration.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a III-N compound semiconductor heterojunction bipolar transistor (HBT) structure and method of manufacture. The method requires no reactive ion etching (RIE) process to expose a portion of the surface of a P-type gallium nitride material layer in order to form the base terminal of a HBT structure. Thus, the surface of the P-type gallium nitride layer is better preserved to form a metal electrode having a better ohmic contact.
A second object of this invention is to provide a III-N compound semiconductor bipolar transistor structure and method of manufacture capable of producing a device with planar surfaces so that subsequent device integration is facilitated.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a III-N compound semiconductor bipolar transistor structure over a substrate. The structure includes a nucleation layer, a buffer layer, an emitter structure layer, a base layer, an ion implant region, an emitter electrode, a base electrode and a collector electrode. The emitter structure layer further includes an emitter contact layer, a graded emitter layer and an emitter layer. The nucleation layer and the buffer layer are stacked in sequence on top of the substrate. The emitter structure layer containing first type dopants (conductive type) is located above the buffer layer. The base layer having second type dopants (conductive type) is above the emitter structure layer. The base layer also exposes a portion of the emitter contact layer. The ion implant layer is within the base layer. The ion implant layer is doped using dopants that differ from the second type dopants (conductive type) in the base layer. The emitter electrode is attached to the exposed surface of the emitter contact layer. The base electrode is attached to a portion of the surface of the base layer. The collector electrode is attached to the surface of the ion implant region. The emitter contact layer is above the buffer layer. The graded emitter layer is above the emitter contact layer and exposes a portion of the emitter contact layer. The emitter layer is between the graded emitter layer and the base layer.
This invention also provides an alternative III-N group compound based semiconductor bipolar transistor structure over a substrate. The structure includes a nucleation layer, a buffer layer, an emitter layer, a base layer, a first ion implant region, a second ion implant region, an emitter electrode, a base electrode and a collector electrode. The nucleation layer and the buffer layer are stacked in sequence on top of the substrate. The emitter layer having first type dopants (conductive type) such as N-type dopants is located above the buffer layer. The base layer having second type dopants (conductive type) such as P-type dopants is located above the emitter layer. The first and the second ion implant region are located within the base layer. The first ion implant layer is formed in the base layer having a depth of implant shallower than the thickness of the base layer. The first ion implant layer is doped using dopants that differ from the second type dopants (conductive type) in the base layer, that is, N-type dopants. The second ion implant region is buried within the base layer but has an implant depth greater than the thickness of the base layer and reaches the emitter layer. Similarly, the second ion implant layer is also doped using dopants that differ from the second type dopants (conductive type) in the base layer, that is, N-type dopants. The emitter electrode is above the second ion implant region, the base electrode is above the base layer and the collector electrode is above the first ion implant region.
This invention provides a method of forming a III-N compound semiconductor bipolar transistor structure. First, a substrate is provided. A nucleation layer and a buffer layer are sequentially formed over the
J.C. Patents
Kang Donghee
South Epitaxy Corporation
Thomas Tom
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