IGFET Decode circuit using series-coupled transistors

Details IGFET Decode circuit using series-coupled transistors IGFET Decode circuit using series-coupled transistors

1979-07-27

1981-09-29

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307304, 307DIG5, 357 68, 365230, H03K 19094, G11C 800, H01L 2952

Patent

active

042925479

ABSTRACT:
A decoder circuit suitable for integrated circuit implementation using IGFET processing is disclosed which may be implemented in a highly dense structure. The decoder output lines are grouped in pairs and at least one of the output lines in each pair is discharged as determined by a bit in the input address. A plurality of IGFET devices under the control of the remaining input address bits selectively couple together the two output lines in each pair such that both output lines can then become discharged. Series-coupled pairs of IGFET devices are used in place of a single IGFET device in order to reduce the chip area required to implement the decoder structure.

REFERENCES:
patent: 3665473 (1972-05-01), Heimbigner
patent: 4094012 (1978-06-01), Perlegos
patent: 4099162 (1978-07-01), Basse
patent: 4103349 (1978-07-01), Marmet
patent: 4124900 (1978-11-01), Smith et al.
Faggin et al., "Silicon Gate Technology"; Solid-State Electronics, Pergamon Press; vol. 13, No. 8, pp. 1125-1144; 1970.

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