IGFET Clock generator circuit employing MOS boatstrap capacitive

Details IGFET Clock generator circuit employing MOS boatstrap capacitive IGFET Clock generator circuit employing MOS boatstrap capacitive

1980-03-21

1982-10-05

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307578, 307601, 307605, H03K 501, H03K 505, H03K 1710, H03K 17284

Patent

active

043529968

ABSTRACT:
A random access read/write MOS memory device or the like employs a clock driver circuit which includes a push-pull type output stage with two transistors having a clock .PHI. and its complement .PHI. as gate inputs. An output node is pulled to a full supply voltage level by a pump transistor connecting the output node to the supply and having a delayed clock coupled to its gate. Another transistor with the supply voltage on its gate connects the output node to the gate of the pump transistor.

REFERENCES:
patent: 3774055 (1973-11-01), Bapat
patent: 3835457 (1974-09-01), Yu
patent: 4061933 (1977-12-01), Schroeder et al.

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