Fishing – trapping – and vermin destroying
Patent
1992-03-13
1993-03-02
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 29, 437 40, 437 41, 437203, 437249, 257139, 257142, 257156, H01L 2100, H01L 2102, H01L 21467
Patent
active
051908859
ABSTRACT:
For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay. P+ doping beneath and marginally surrounding the gate pads and main gate bus negates breakdown conditions in widely spaced body regions and convex localities at the source finger end. Wide secondary gate buses parallel to the gate fingers have a P+ doped central stripe and transverse shorting bars spaced along their length. A non-polarizable PECVD passivation film of low phosphorus PSG and nitride or oxynitride or of oxynitride alone is made by controlling ionized gas residence time, silane partial pressure, and oxygen ratio during deposition, to minimize incorporation of Si-H into the film.
REFERENCES:
patent: 3206670 (1965-01-01), Atalla
patent: 3210563 (1965-10-01), New
patent: 3324359 (1967-06-01), Gentry
patent: 3675313 (1972-07-01), Driver et al.
patent: 4199774 (1980-04-01), Plummer
patent: 4345265 (1982-08-01), Blanchard
patent: 4364073 (1982-12-01), Becke et al.
patent: 4399449 (1983-08-01), Herman et al.
patent: 4417385 (1983-11-01), Temple
patent: 4443931 (1984-04-01), Baliga
patent: 4453305 (1984-06-01), James et al.
patent: 4497107 (1985-02-01), Cogan
patent: 4503598 (1985-03-01), Vora et al.
patent: 4553316 (1985-11-01), Houston
patent: 4586243 (1986-05-01), Weaver et al.
patent: 4587713 (1986-05-01), Goodman et al.
patent: 4689647 (1987-08-01), Nakagawa et al.
patent: 4766094 (1988-08-01), Hollinger
patent: 4778774 (1988-10-01), Blossfeld
patent: 4789643 (1988-12-01), Kajikawa
patent: 4809045 (1989-02-01), Yilmaz
patent: 4857476 (1989-08-01), Colinge
patent: 4895810 (1990-01-01), Meyer et al.
patent: 4980302 (1990-12-01), Shimizu
patent: 4994400 (1991-02-01), Yamaguchi et al.
patent: 5045903 (1991-09-01), Meyer et al.
Wheatley, COMFET-The Ultimate Power Device: A General Study of Power Devices, Sol. State Tech., Nov. 1985, pp. 121-128.
Tihanyi, Functional Integration of Power MOS and Bipolar Devices, IEEE, 1980, pp. 75-80.
Miller, M. D., Differences Between Platinum- and Gold-Doped Silicon Power Devices, IEEE Transactions on Electron Devices, vol. ED-23, No. 12, Dec. 1976.
Ohmi, Power Static Induction Transistor Technology, IEDM, pp. 84-87, FIG. 7, 1979.
Baliga, Power Junction Gate Field Controlled Devices, IEDM, pp. 76-78, 1979.
Plummer et al, Insulated Gate Planar Thyristors: I-Structure and Basic Operation; II-Quantitative Modeling, IEEE Trans. Electron Devices, ED-27 pp. 380-394, 1980.
Leipold et al, A FET-Controlled Thyristor in SIPMOS Technology, IEDM pp. 79-82, 1980.
Laska, T. et al, A 2000 V-Non-Punch-Through-IGBT with Dynamical Properties like a 1000 V-IGBT, IEDM, pp. 807-810, 1990.
Lisiak et al, Platinum as a lifetime-control deep impurity in silicon, J. Appl. Phys. vol. 46, No. 12, pp. 5229-5235, Dec. 1975.
Baliga et al, The Insulated Gate Rectifier (IGR): A New Power Switching Device, IEDM pp. 264-267, 1982.
Russell et al, The COMFET--A New High Conductance MOS Gated Device, IEEE Electron Device Lett., EDL-4, pp. 63-65, 1983.
Kuo et al., Modeling The Turn-off Characteristics of the Bipolar-MOS Transistor, IEEE Electron Device Lett., EDL-6, pp. 211-214, 1985.
Kuo and Hu, Optimization of Epitaxial Layers for Power Bipolar-MOS Transistor, IEEE Electron Device Lett., EDL-7, pp. 510-512, 1986.
Lorenz, Selection Criteria for Power Semiconductor for Motor Drives, Proceedings of 1990 International Symposium on Power Semiconductor Devices & ICs, Tokyo, pp. 263-269, 1990.
Tsunoda et al., Improved 600- and 1200-V IGBT with Low Turn-off Loss and High Ruggedness, Proceedings of the Power Electronics Specialists Conference, San Antonio, Tex., pp. 9-16, Jun. 1990.
Baliga, Modern Power Devices, Ch. 7 and 8, 1987.
Shekar, M. S. et al, Characteristics of the Emitter-Switched Thyristor, IEEE Transactions on Electron Devices, ED-38, No. 7, pp. 1619-1623, Jul. 1991.
Nakagawa, A. et al, Non-Latchup 1200V 75A Bipolar-Mode MOSFET with Large ASO, IEDM, pp. 860-861, 1984.
Petterteig et al, Digest of Paper given at EPE-MADEP Conference, Florence, Italy, 1991.
Temple et al., Optimizing Carrier Lifetime Profile for Improved Tradeoff Between Turn-Off Time and Forward Drop, IEEE Transactions on Electron Devices, vol. ED-30, No. 7, pp. 782-790, Jul. 1983.
Temple, MOS-Controlled Thyristors-A New Class of Power Devices, IEEE Transactions on Electron Devices, ED-33, No. 10, pp. 1609-1618, Oct. 1986.
Hashimoto et al., Properties of PEVD SiOxNy Films as Selective Diffusion Barrier, J. Electrochem. Soc., vol. 133, No. 7, pp. 1464-1467.
Katana James M.
Pike, Jr. Douglas A.
Tsang Dah W.
Advanced Power Technology Inc.
Everhart B.
Hearn Brian E.
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