Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – Including additional component in same – non-isolated structure
Reexamination Certificate
2001-01-09
2002-08-27
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
Including additional component in same, non-isolated structure
C257S572000, C307S131000
Reexamination Certificate
active
06441463
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device in which an insulated gate bipolar transistor and a control circuit are formed on a same semiconductor substrate. In particular, it relates to a construction of a protection device or protection circuit for preventing latch-up due to a parasitic device which occurs on the occasion of forming the control circuit on the insulated gate bipolar transistor using the joining and separating technique.
2. Description of the Prior Art
In general, when a circuit region or circuit element etc. is formed on a semiconductor substrate in which an insulated gate bipolar transistor (Hereinafter, it will be referred to “IGBT”.) is formed, a parasitic device which deteriorates the properties of the circuit, may occur. Therefore it has been tried to provide various methods of forming the circuit region or circuit element etc. which can restrain the action of the parasitic device.
For example, in the technical field for forming the circuit region by means of the joining and separating technique without using a particular technique for forming the substrate, a method of forming the above-mentioned circuit region or circuit device etc. is disclosed in the technical document of “A Self-isolated Intelligent IGBT for Driving Ignition Coils (International Symposium on Power Semiconductor Drives & Ics, 1998)” published in 1998. In the technical document, there is disclosed such a means for preventing a breakdown of the device by using a circuit in which a resistor and a diode formed on a polycrystalline silicon layer are combined, in order to avoid the breakdown of the circuit due to the action of a parasitic thyristor which may cause a fatal problem in the joining and separating technique.
Meanwhile, in each of the Japanese Laid-open Patent Publications No. 7-169963, No. 8-306924 and No. 64-51664 also, there is disclosed a technique for restraining the action of a parasitic device in a semiconductor device provided with an IGBT or MOSFET.
In
FIG. 9
, there is partially shown a conventional circuit for preventing the action of a parasitic thyristor, which is disclosed in the above-mentioned technical document. In
FIG. 9
, P
1
denotes an input terminal for controlling a semiconductor device B
2
in which a control circuit B
1
is formed on a semiconductor substrate in which an IGBT Z
1
is formed. P
2
denotes an emitter terminal of the IGBT Z
1
, which acts as the ground terminal of the control circuit B
1
also. P
3
denotes a collector terminal of the IGBT Z
1
.
The input terminal P
1
is connected to the cathode of a Zener diode D
1
through a resistor R
1
. On the other hand, the anode of the Zener diode D
1
is connected to the emitter terminal P
2
. Further the cathode of the Zener diode D
1
is also connected to one end portion of a resistor R
2
. The other end portion of the resistor R
2
is connected to one end portion of a resistor R
3
and to the cathode of a Zener diode D
8
. The other end portion of the resistor R
3
is connected to the control circuit B
1
. Meanwhile the anode of the Zener diode D
8
is connected to the emitter terminal P
2
.
Each of the resistors R
2
, R
3
and the diodes D
1
, D
8
is formed on a polycrystalline silicon layer (Hereinafter, it will be referred to “polysilicon layer”.) formed above the substrate in which the IGBT Z
1
is formed, while interposing an insulating film therebetween. In the device described in the above-mentioned technical document, the control circuit B
1
for controlling the IGBT Z
1
is composed of a nch-MOSFET (of enhancement mode or depletion mode)
In
FIG. 10
, there is shown a construction each of parasitic thyristors of a circuit device in the conventional semiconductor device described above. As shown in
FIG. 10
, parasitic transistors T
1
, T
2
are formed between each of diffused layers of an nch-MOSFET M and a semiconductor substrate U composing the diffused layers. A p
−
type diffused region corresponding to the back gate G of the nch-MOSFET M, an n type diffused layer formed so as to be included in this p
−
type diffused region (It corresponds to the source S or drain A of the nch-MOSFET M) and an n
−
type layer of the semiconductor substrate U act as the base, emitter and collector of the npn type parasitic transistor T
2
, respectively. Meanwhile, a p type layer of the semiconductor substrate U, n
+
and n
−
type layers formed on this p type layer and a p
−
type diffused layer corresponding to the back gate G of the nch-MOSFET M act as the emitter, base and collector of the pnp type parasitic transistor T
1
, respectively.
The parasitic transistors T
1
, T
2
become such a state that the collector of the parasitic transistor T
1
is connected to the base of the parasitic transistor T
2
while the base of the parasitic transistor T
1
is connected to the collector of the parasitic transistor T
2
, so that a thyristor is formed. In consequence, if the thyristor has become ON state once, it is impossible to make the thyristor become OFF state except making such a state that the collector potential of the IGBT M becomes lower than the emitter potential of the IGBT M.
As patterns that the thyristor becomes ON state, the following two patterns may be estimated. One is such a case that the source potential of the nch-MOSFET M becomes lower than the back gate potential so that emitter current is generated in the npn type parasitic transistor T
1
. The other is such a case that the pnp type parasitic transistor T
1
becomes ON state in accordance with the ON state of the IGBT M formed on the same substrate. In this case, the collector current of the pnp type parasitic transistor T
1
flows into the back gate G of the nch-MOSFET M so that the potential of the back gate G is lowered. In consequence, when it becomes higher than the potential of the source S or drain A of the nch-MOSFET M, latch-up occurs as same as the case described above.
In particular, if an interface for the outer device of the semiconductor device is provided as the input terminal P
1
, it may be more probable that the potential of the input terminal P
1
becomes lower than the potential of the emitter terminal P
2
. Although its period is shorter than the period to cause a surge, it is estimated that a larger stress may be applied to it due to a momentary current. Therefore, in this case also, it is probable that latch-up is caused.
So, when the protection circuit for protecting the input terminal P
1
shown in
FIG. 9
is used, it is prevented that parasitic devices occur between the protection circuit and the semiconductor substrate, by making the whole protection circuit as a device formed on the polysilicon. Thus, the emitter current flowing through the npn type parasitic transistor T
2
is restrained by effects on the circuit so that it is prevented that the parasitic thyristor causes latch-up.
When the device is actually formed, a resistor R
3
is certainly disposed in series for the npn type parasitic transistor T
2
in which the source S or drain A of the nch-MOSFET M formed in the control circuit B
1
acts as the emitter of the transistor T
2
. Thus it is restrained that the voltage between the resistor R
3
and the emitter of the npn type parasitic transistor T
2
is lowered, because the voltage of the Zener diode D
8
in the forward direction is lowered. Similarly, it is designed such that the current of the circuit composed of the Zener diode D
8
, the resistor R
3
and the control circuit B
1
passes through the resistor R
2
connected in series thereto. Thus the voltage drop caused in the above-mentioned circuit due to the resistor R
2
is restrained, because the voltage of the Zener diode D
1
in the forward direction is lowered.
In the conventional technique described above, the current flowing the parasitic device is restrained due to the voltage drop of the diode in the forward direction and the voltage drop at the series resistor in the circuit connected to the diode in parallel. Therefore, the vo
Ho Tu-Tu
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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