IEEE Std. 1149.1 boundary scan circuit capable of built-in self-

Details IEEE Std. 1149.1 boundary scan circuit capable of built-in self- IEEE Std. 1149.1 boundary scan circuit capable of built-in self-

1995-05-10

1996-10-29

Canney, Vincent P.

Excavating

39518306, G01R 3128

Patent

active

055703755

ABSTRACT:
An IEEE Std. 1149.1 boundary scan circuit which is capable of performing built-in self-testing includes a logic circuit, cascaded input boundary-scan cells that form an input boundary-scan register connected to input nodes of the logic circuit, cascaded output boundary-scan cells that form an output boundary-scan register connected to output nodes of the logic circuit, and a test access port system for controlling operation of the input and output boundary-scan cells. The test access port system provides a built-in self-test control signal to the input and output boundary-scan cells when executing built-in self-testing. The input boundary-scan register is reconfigurable to operate as a test pattern generator that provides test patterns to the logic circuit for a predetermined number of clock cycles upon receipt of the built-in self-test control signal. The output boundary-scan register is reconfigurable to operate as an output response analyzer that is driven by the logic circuit for the predetermined number of clock cycles upon receipt of the built-in self-test control signal. A family of input and output boundary-scan cells that can be reconfigured as a linear feedback shift register and as a multiple-input shift register is also disclosed.

REFERENCES:
patent: 5042034 (1991-08-01), Correale, Jr. et al.
C. S. Gloster & F. Brglez, 1988 Int'l Test Conf., Paper 7.2:138-145 (1988).
C. S. Gloster & F. Brglez, IEEE Design & Test Of Computers, (Feb. 1989):36-44.
C. W. Yau & N. Jawala, 1990 Int'l Test Conf., Paper 16.3:311-315 (1990).
N. jarwala and B. W. Yau, 1991 Int'l Test Conf., Paper 243:649-658.
T. Langford, Int'l Test Conf., 1993 Paper 6.2:167-173.

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