IEEE compliant floating point unit

Details IEEE compliant floating point unit IEEE compliant floating point unit

1998-02-19

2000-03-28

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Architecture based instruction processing

Data flow based system

712244, 712227, 712222, 39550047, G06F 9302, G06F 938

Patent

active

060444541

ABSTRACT:
IEEE compliant floating point unit mechanism allows variability in the execution of floating point operations according to the IEEE 754 standard and allowing variability of the standard to co-exist in hardware or in the combination of hardware and millicode. The FPU has a detector of special conditions which dynamically detects an event that the hardware execution of an IEEE compliant Binary Floating Point instruction will require millicode emulation. The complete set of events which millicode may emulate are predetermined early in the design process of the hardware. An exception handling unit assist millicode emulation by trapping the result of an exceptional condition without invoking the trap handler. When an exceptional condition is detected during execution, the IEEE 754 standard requires two different actions under control of a mask bit. If the mask bit is on, the result is written into an FPR and the trap handler is invoked. Otherwise, a default value is written, a flag is set, and the program continues execution. This allows a variation to the IEEE 754 standard. Two different versions of the function of the Multiply-then-Substract instruction are implemented for two different IEEE 754 compliant architectures.

REFERENCES:
patent: 5438670 (1995-08-01), Baror et al.
patent: 5799179 (1998-08-01), Ebcioglu et al.
"When Floating-Point Addition Isn't Commutative" by F. Ris et al., Jan. 27, 1993, IBM Federal System Co., Boulder, Co, pp. 8-13.
"On the Design of IEEE Compliant Floating Point Units" by G. Even and W. Paul, 1997 IEEE 1063-6889/97, pp. 54-63.
"What Causes A Trap In IEEE-754 Floating Point?" by Fred Tydeman, IBM Corporation, Austin, TX, pp. 2-5.
"Implementation of Binary Floating Point Architecture to Enable Efficient Emulation of Single and Double Precision Arithmetic" IBM Technical Disclosure Bulletin, by Rodriquez, vol. 31, No. 3,Aug. 1988, p4-9.
"Floating Point Exception Handling (Denormalization)" IBM Technical Disclosure Bulletin, by Goldberg et al., vol. 33, No. 9, Feb. 1991, p345-348.
"Floating-Point Vector Microcode Exception Emulation" IBM Technical Disclosure Bulletin, by Vanover et al., vol. 34, No. 7B, Dec. 1991, p466-468.
"Round-Up Anticipator for IEEE Floating Point Standard-754" IBM Technical Disclosure Bulletin, by Atkins, vol. 36, No. 10, Oct. 1993, p141-144.

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