Coded data generation or conversion – Converter compensation
Reexamination Certificate
1999-05-11
2002-02-19
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S141000, C341S144000, C341S155000
Reexamination Certificate
active
06348884
ABSTRACT:
2 BACKGROUND—FIELD OF INVENTION
The field of invention is data conversion, more precisely, this invention relates to oversampled mismatch-shaping digital-to-analog converters.
3 BACKGROUND—DESCRIPTION OF PRIOR ART
In electronic circuits, signal processing is most efficiently implemented when the signals are represented digitally. Real-world signals are analog, and the conversion between analog and digital signals is, therefore, an important application. The following discussion centers around the implementation of digital-to-analog (D/A) converters, which may be used either directly for the D/A conversion of digital signals, or as an important element for the implementation of analog-to-digital (A/D) converters.
3.1 Binary-Weighted D/A Converters
A thorough discussion of the ideal operation of and several techniques for the implementation of D/A converters can be found in a Ph.D. thesis by Jesper Steensgaard [
High-Performance Data Converters,
Ph.D. thesis by Jesper Steensgaard, Jan. 20, 1999, The Technical University of Denmark, Lyngby Denmark]. D/A converters are often implemented by separating the digital input signal d(k) into a sum of digital subsignals d(k)=d
1
(k)+d
2
(k)+. . . +d
N
(k) which are D/A converted individually, thereby generating the analog subsignals a
1
(k),a
2
(k), . . . , a
N
(k). The overall analog output signal a(k) is the sum of the analog subsignals, a(k)=a
1
(k)+a
2
(k)+. . . +a
N
(k). In the ideal case, the analog subsignals are proportional to the corresponding digital subsignals, i.e. a
i
(k)=Kd
i
(k), i&egr;{1, 2, . . . , N}, where K is the same dimensional constant (for example 1 milli Volt or 1 micro Ampere) for all the subsignals. In that case the operation is considered to be ideal a(k)=Kd(k). Offsets are often acceptable.
For ease of implementation, the digital subsignals will typically be of low resolution, i.e., the digital subsignals d
i
(k) are sequences of values selected from sets S
i
consisting of each only a few elements. For example, binary-weighted D/A converters are very simple D/A converters that separate the digital input signal d(k) bitwise into digital subsignals d
i
(k), which each attain only two values, S
i
={0, k
i
}, the difference of which, k
i
, is proportional to a power of two, 2
i
. Binary-weighted D/A converters operate by letting each two-level digital subsignal turn on or off an analog source which is scaled according to k
i
, whereby the analog subsignals a
i
(k) are generated. To simplify the summation of the analog subsignals, the analog sources will typically be charge or current sources.
FIG. 1
shows a typical 4-bit binary-weighted current-steering D/A converter with gain K=1 mA.
3.2 Errors Caused by Mismatch of the Analog Sources
Electrical parameters are unfortunately not well controlled in the processing of integrated electrical circuits. Thus, the gains K
i
of the sub D/A converters will generally not all attain their nominal value K, nor will they match perfectly their nominal ratios. This implies that a typical binary-weighted D/A converter is not fully described by the gain factor K because, for any gain value {circumflex over (K)}, the error e(k)=a(k)−d(k){circumflex over (K)} will be a nonconstant function of the digital input signal d(k). In other words, the D/A converter is characterized by a nonlinear behavior, which is undesirable.
FIG. 2
shows an example of an unit-element D/A converter. Unit-element D/A converters have the property that the digital input signal d(k) is separated into digital subsignals d
i
(k) which all attain only values from the same set S consisting of only two elements, say 0 and 1. Hence, the analog sources used to implement the sub D/A converters all have the same nominal value; they are called unit elements. Unit-element D/A converters based on deterministic and time-invariant digital encoders [
32
] are characterized by a good local linearity (the so-called differential nonlinearity), but the overall/absolute linearity (the so-called integral nonlinearity) is equivalent to that of binary-weighted D/A converters.
3.3 Mismatch-Matching D/A Converters
As opposed to binary-weighted D/A converters, the digital subsignals d
i
(k) used in unit-element D/A converters are not necessarily uniquely defined functions of the digital input signal d(k). Consider the 5-level unit-element D/A converter shown in FIG.
2
. If, for example, the digital input signal d(k) has the value 1, then the digital encoder [
32
] can assign the value 1 to any one of the 4 digital subsignals d
i
(k), and thus, assign the value 0 to the other 3 digital subsignals. In other words, for d(k)=1, the correct nominal operation can be achieved in 4 different ways. Similarly, when the digital input signal d(k) has either the value 2 or 3, the nominal operation can be achieved in respectively 6 and 4 different ways. The digital subsignals d
i
(k) are uniquely defined when the value of the digital input signal d(k) is either 0 or 4.
D/A converters, for which the nominally correct analog output signal can be generated in multiple ways, and for which harmonic distortion due to mismatch of electrical parameters is avoided by alternating between the multiple options, are said to be mismatch-shaping.
3.3.1 Randomized-Scrambling Encoders
L. Richard Carley explained [“A Noise-Shaping Coder Topology for 15+ Bit Converters”, L. Richard Carley,
IEEE Journal of Solid
-
State Circuits,
Vol. 24, No. 2, April 1989] that if the digital encoder [
32
] for every new input sample selects randomly one of the valid combinations, then the unit-element D/A converter will be perfectly linear. Carley proposed an implementation, shown in
FIG. 3
, where a thermometer-type digital encoder [
36
] is followed by a butterfly-type randomizing scrambler [
38
]. The thermometer-type digital encoder [
36
] generates the digital intermediate signals, b
1
(k), b
2
(k), b
3
(k), and b
4
(k), according to the deterministic, memoryless, and time-invariant operation expressed by the truth table shown in FIG.
4
. The randomizing scrambler [
38
] generates the digital subsignals d
i
(k) by randomly (or, more generally, pseudo-randomly) interchanging the intermediate signals b
i
(k). In other words, the subsignals are randomly generated permutations of the intermediate signals. Carley explained that a unit-element DAC based on this type of randomized-scrambling digital encoder [
34
] will be perfectly linear and have a gain which is exactly the average value of the employed sub D/A converters' gains.
Instead of harmonic distortion, the overall analog output signal a(k) will include a stochastic signal component e(k) (noise) having uniform spectral power density (similar to white noise). The Nyquist-band power of e(k) is proportional to the mismatch of the employed analog sources. For example, if the relative mismatch of the analog sources is in the order of 0.1%, which is a typical value, then the analog output signal a(k) will have a signal-to-noise ratio (SNR) of approximately 60 dB when evaluated in the Nyquist frequency range. Usually D/A converters are operated somewhat oversampled, i.e., the sampling frequency f
s
is usually more than twice the considered signal bandwidth f
b
, in which case the inband SNR will be somewhat better than 60 dB. However, the inband SNR performance is improved only 10 dB for each ten-fold increase of the oversampling ratio (OSR=f
s
/(2f
b
)). Thus, 100 dB performance requires in the order of 10,000 times oversampling, which usually is not feasible.
Randomized-scrambling unit-element encoders are said to be zero-order mismatch-shaping because the error signal is not suppressed in the signal band.
3.3.2 Element-Rotation-Scheme (ERS) Encoders
U.S. Pat. No. 5,138,317 to Michael J. Story describes that by generating the digital subsignals as a certain function of the present and previous
LandOfFree
Idle-tone-free mismatch-shaping encoders does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Idle-tone-free mismatch-shaping encoders, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Idle-tone-free mismatch-shaping encoders will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2950169