Patent
1995-08-28
1999-03-23
Kim, Kenneth S.
39518315, 39518501, 395557, 39575004, G06F 132
Patent
active
058871780
ABSTRACT:
An instruction address that is referred to by a microprocessor unit is inputted over an instruction address bus and is stored. While counting the number of times a clock is fed to the microprocessor unit, a comparison is made between the stored instruction address and an instruction address that the microprocessor provides onto the instruction address bus. A clock count value, obtained at the time when the aforesaid instruction addresses agree, is stored. If a stored instruction address and an instruction address on the instruction address bus agree for every stored clock count value, then the microprocessor is judged to repeatedly execute a sequence of instructions and the loop count value is incremented by one. When the loop count value exceeds a predetermined value, the microprocessor is judged to be placed in an idle state and the clock frequency is lowered.
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patent: 4879647 (1989-11-01), Yazawa
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Nikkei Electronics, Jul. 5, 1993 (No. 585) pp. 172-178 and English Abstract .
Ohtani Akihiko
Ozaki Shinji
Sugimura Toshio
Tsujimoto Taizou
Kim Kenneth S.
Matsushita Electronics Corporation
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