Idle address controller for shared buffer type ATM switch

Details Idle address controller for shared buffer type ATM switch Idle address controller for shared buffer type ATM switch

1997-06-13

2000-02-08

Vu, Huy D.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

H04L 1254

Patent

active

060234695

ABSTRACT:
An idle address controller for a shared buffer type ATM switch controls the addresses of output cells in a common memory to be stored directly in an idle address buffer without passing through the conventional idle address delay controller, by improving the idle address control scheme of a unit switch. The idle address controller includes an idle address control signal generator for generating idle address control signals based on the buffer length information from counters, idle address control signal buffers for storing the idle address control signals, and an idle address control signal multiplexer. Therefore, the idle addresses can be efficiently provided, and this mechanism lowers cell loss and reduces required memory capacity.

REFERENCES:
patent: Re34305 (1993-07-01), Sakurai et al.
Wu, Jung-Shyr, et al. ATM Shared Memory Switch and Multicasting Balancing, IEICE Trans. Commun. vol. E78-B, No. 9, Sep. 1995.
Wu, Jung-Shyr, et al. Traffic Management Circuit for the Shared Buffer Memory Switch with Multicasting, Computer Communications, vol. 16, No. 11, Nov. 1993.
Endo, Noboru, et al. Shared Buffer Memory Switch for an ATM Exchange, IEEE Transactions on Communications, vol. 41, No. 1, Jan. 1993.

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