Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2007-01-17
2009-02-24
Garber, Charles D. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
Reexamination Certificate
active
07494893
ABSTRACT:
In one embodiment, wafers are processed to build test structures in the wafers. The wafers may be processed in tools of process steps belonging to a process module. The test structures may be tested to obtain defectivity data. Tool process parameters may be monitored and collected as process tool data. Other information about the wafers, such as metrology data and product layout attribute, may also be collected. A model describing the relationship between the defectivity data and process tool data may be created and thereafter used to relate the process tool data to a yield of the process module. The model may initially be an initial model using process tool data from a limited number of test wafers that contain test structures. The model may also be an expanded model using process tool data from product wafers containing embedded test structures in areas with no product devices.
REFERENCES:
patent: 6449749 (2002-09-01), Stine
patent: 6470229 (2002-10-01), Wang et al.
patent: 6475871 (2002-11-01), Stine et al.
patent: 6587744 (2003-07-01), Stoddard et al.
patent: 6594618 (2003-07-01), Azencott
patent: 6714884 (2004-03-01), Dor et al.
patent: 6721445 (2004-04-01), Azencott
patent: 6725098 (2004-04-01), Edwards et al.
patent: 6787800 (2004-09-01), Weiland et al.
patent: 6795952 (2004-09-01), Stine et al.
patent: 6804563 (2004-10-01), Lafaye de Michaeaux
patent: 6826738 (2004-11-01), Cadouri
patent: 6834375 (2004-12-01), Stine et al.
patent: 6853923 (2005-02-01), Trygg et al.
patent: 6892367 (2005-05-01), Palusinski et al.
patent: 6901564 (2005-05-01), Stine et al.
patent: 6970857 (2005-11-01), Card et al.
patent: 6978229 (2005-12-01), Saxena et al.
patent: 7003742 (2006-02-01), Saxena et al.
patent: 7016816 (2006-03-01), Mott
patent: 7024642 (2006-04-01), Hess et al.
patent: 7039543 (2006-05-01), Cadouri
patent: 7047505 (2006-05-01), Saxena et al.
patent: 7072985 (2006-07-01), Lev-Ami et al.
patent: 7087507 (2006-08-01), Koldiaev et al.
patent: 2002/0072162 (2002-06-01), Dor et al.
patent: 2003/0220708 (2003-11-01), Sahin et al.
patent: 2006/0111804 (2006-05-01), Lin
patent: 2006/0246683 (2006-11-01), Pan et al.
patent: 1 122 646 (2001-08-01), None
patent: 1 170 650 (2002-01-01), None
Andrzej J. Strojwas, et al. “Conquering Process Variability: A Key Enabler for Profitable Manufacturing in Advanced Technology Nodes (Keynote Speech)”, Sep. 2006, 8 sheets, International Symposium On Semiconductor Manufacturing (ISSM), Tokyo, Japan.
Christopher Hess, et al. “Yield Improvement Using a Fast Product Wafer Level Monitoring System”, May 2006, 5 sheets, 17thAnnual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC), Boston, MA.
David Abercrombie “Applying Effective Design for Manufacturing Techniques in Nanometer Technology”, Apr. 10, 2006, pp. 1-41, EDATF, Mentor Graphics.
Dennis Ciplickas, et al. “Designing for High Product Yield” Oct. 1, 2002, pp. 1-6, PDF Solutions Inc, Semiconductor International [retrieved on Oct. 24, 2006]. Retrieved from the internet: http://www.reed-electronics.com/semiconductor/index.asp?layout=articlePrint&articleID=CA245210.
Principal components analysis—Wikipedia, the free encyclopedia, pp. 1-11, [retrieved on Oct. 25, 2006]. Retrieved from the internet: http://en.wikipedia.org/wiki/Principal—components—analysis.
Regression analysis—Wikipedia, the free encyclopedia, pp. 1-9, [retrieved on Oct. 25, 2006]. Retrieved from the internet: http://en.wikipedia.org/wiki/Regression—analysis.
Arthanari Senthil
Graves Spencer B.
Inani Anand
Liao Marci Yi-Ting
Stine Brian E.
Garber Charles D.
Okamoto & Benedicto LLP
PDF Solutions, Inc.
Stevenson Andre′ C
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