Identifying an optimizable logic region in a logic network

Details Identifying an optimizable logic region in a logic network Identifying an optimizable logic region in a logic network

1996-12-09

2000-01-25

Teska, Kevin J.

G06F 1750

Patent

active

060186216

ABSTRACT:
At least one certain type of logic gates, such as NOT gates, in a network of logic gates are moved to the network inputs and outputs, by converting the logic gates in the network to certain types of gates, such as AND, OR and NOT gates. A region in the network is identified for selecting, within the region, between propagating the one certain type of gates to a) the network inputs, and b) the network outputs. The region is identified in response to "reconvergent fanout nodes". A reconvergent fanout node defines a loop having two branches which diverge at the node and reconverge thereafter.

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