Patent
1996-10-21
1998-06-16
Chan, Eddie P.
395469, 395471, 395473, G06F 1208
Patent
active
057685584
ABSTRACT:
A computer system includes a microprocessor having an internal cache memory and control unit that performs write-back operations to external memory responsive to an external signal indicating that a valid external address has been driven onto the address pins of the microprocessor. Under control of a state machine control, a unit within the microprocessor provides an indication signal to the external component that a current write cycle is a write-back cycle; this enables the system to distinguish between an ongoing write cycle generated by the processor, and a new write-back cycle. An additional signal is generated by the microprocessor in the event that the external address indicates a cache hit to a modified line.
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Choudhury Mustafiz R.
Iyengar Sundaravarathan R.
Bragdon Reginald G.
Chan Eddie P.
Intel Corporation
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