Identification of a faulty address decoder in a function unit of

Details Identification of a faulty address decoder in a function unit of Identification of a faulty address decoder in a function unit of

1977-12-29

1979-08-21

Chapnick, Melvin B.

Boots, shoes, and leggings

235307, 235312, G06F 1106

Patent

active

041655338

ABSTRACT:
A central control unit is connected via a common bus system to a number of function units, each of which being furnished with redundant address decoders in order to ensure reliable selection of the function units. If, in response to an address which is sent out by the control unit, a signal is emitted by only one of the two address decoders of a function unit, a recording is made in a memory device corresponding to that decoder to indicate an erroneous condition in one of the address decoders of the addressed function unit. If, on the other hand, signals are emitted by both address decoders a check signal is returned to the control unit, the absence of the check signal indicating that either one of the decoders belonging to the addressed function unit is faulty. Error recordings are read out from the respective memory device by subsequent addressing of the units, the read out from the memory device belonging to the one address decoder being effected by the signal emitted by the other decoder and vice versa.

REFERENCES:
patent: 3177468 (1965-04-01), Ruoff
patent: 3476922 (1969-11-01), Yiotis
patent: 3609704 (1971-09-01), Schurter
Bardsley et al., "Invalid Address Detector" in IBM Technical Disclosure Bulletin, vol. 9, No. 8, Jan. 1967, pp. 986-987.
Duke et al., "Fail-Safe Storage Cell" in IBM Technical Disclosure Bulletin, vol. 11, No. 10, Mar. 1969, pp. 1229-1230.
McMahon, "AC Test Procedure for Redundant Functional Islands" in IBM Technical Disclosure Bulletin, vol. 16, No. 11, Apr. 1974, p. 3597.
Iosupovicz, "Adaptive Universal Fault-Tolerant Logic Networks" in IEEE Transactions on Computers, Oct. 1975, pp. 1043-1048.

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