Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth with a subsequent step acting on the...
Reexamination Certificate
2001-08-13
2003-03-25
Kunemund, Robert (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Processes of growth with a subsequent step acting on the...
C117S003000, C117S089000, C117S094000, C117S095000, C117S935000
Reexamination Certificate
active
06537368
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to the preparation of semiconductor material substrates, especially silicon wafers, which are used in the manufacture of electronic components. More particularly, the present invention relates to a process for the treatment of silicon wafers which enables the wafers, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates.
Single crystal silicon, which is the starting material for most processes for the fabrication of semiconductor electronic components, is commonly prepared with the so-called Czochralski process wherein a single seed crystal is immersed into molten silicon and then grown by slow extraction. As molten silicon is contained in a quartz crucible, it is contaminated with various impurities, among which is mainly oxygen. At the temperature of the silicon molten mass, oxygen comes into the crystal lattice until it reaches a concentration determined by the solubility of oxygen in silicon at the temperature of the molten mass and by the actual segregation coefficient of oxygen in solidified silicon. Such concentrations are greater than the solubility of oxygen in solid silicon at the temperatures typical for the processes for the fabrication of electronic devices. As the crystal grows from the molten mass and cools, therefore, the solubility of oxygen in it decreases rapidly, whereby in the resulting slices or wafers, oxygen is present in supersaturated concentrations.
Thermal treatment cycles which are typically employed in the fabrication of electronic devices can cause the precipitation of oxygen in silicon wafers which are supersaturated in oxygen. Depending upon their location in the wafer, the precipitates can be harmful or beneficial. Oxygen precipitates located in the active device region of the wafer can impair the operation of the device. Oxygen precipitates located in the bulk of the wafer, however, are capable of trapping undesired metal impurities that may come into contact with the wafer. The use of oxygen precipitates located in the bulk of the wafer to trap metals is commonly referred to as internal or intrinsic gettering (“IG”).
Historically, electronic device fabrication processes included a series of steps which were designed to produce silicon having a zone or region near the surface of the wafer which is free of oxygen precipitates (commonly referred to as a “denuded zone” or a “precipitate free zone”) with the balance of the wafer, i.e., the wafer bulk, containing a sufficient number of oxygen precipitates for IG purposes. Denuded zones can be formed, for example, in a high-low-high thermal sequence such as (a) oxygen out-diffusion heat treatment at a high temperature (>1100° C.) in an inert ambient for a period of at least about 4 hours, (b) oxygen precipitate nuclei formation at a low temperature (600-750° C.), and (c) growth of oxygen (SiO
2
) precipitates at a high temperature (1000-1150° C.). See, e.g., F. Shimura, Semiconductor Silicon Crystal Technology, Academic Press, Inc., San Diego, Calif. (1989) at pages 361-367 and the references cited therein.
More recently, however, advanced electronic device manufacturing processes such as DRAM manufacturing processes have begun to minimize the use of high temperature process steps. Although some of these processes retain enough of the high temperature process steps to produce a denuded zone and sufficient density of bulk precipitates, the tolerances on the material are too tight to render it a commercially viable product. Other current highly advanced electronic device manufacturing processes contain no out-diffusion steps at all. Because of the problems associated with oxygen precipitates in the active device region, therefore, these electronic device fabricators must use silicon wafers which are incapable of forming oxygen precipitates anywhere in the wafer under their process conditions. As a result, all IG potential is lost.
SUMMARY OF THE INVENTION
Among the objects of the invention, therefore, is the provision of a single crystal silicon wafer which, during the heat treatment cycles of essentially any electronic device manufacturing process, will form an ideal, non-uniform depth distribution of oxygen precipitates; the provision of such a wafer which will optimally and reproducibly form a denuded zone of sufficient depth and a sufficient density of oxygen precipitates in the wafer bulk; the provision of such a wafer in which the formation of the denuded zone and the formation of the oxygen precipitates in the wafer bulk is not dependant upon differences in oxygen concentration in these regions of the wafer; the provision of such a process in which the formation of the denuded zone does not depend upon the out-diffusion of oxygen; the provision of such a wafer in which the thickness of the resulting denuded zone is essentially independent of the details of the IC manufacturing process sequence; and the provision of such a wafer in which the formation of the denuded zone and the formation of the oxygen precipitates in the wafer bulk is not influenced by the thermal history and the oxygen concentration of the Czochralski-grown, single crystal silicon ingot from which the silicon wafer is sliced.
Briefly, therefore, the present invention is directed to a Cz single crystal silicon wafer having a front surface, a back surface, a central plane between the front and back surfaces, a front surface layer which comprises the region of the wafer between the front surface and a distance, D
1
, measured from the front surface and toward the central plane, and a bulk layer which comprises the region of the wafer between the central plane and the distance, D
1
, measured from the front surface of the wafer. In addition, the wafer has a non-uniform distribution of crystal lattice vacancies (one type of intrinsic point defect which forms in single crystal silicon) with the concentration of vacancies in the bulk layer being greater than the concentration of vacancies in the front surface layer with the difference in concentration being such that upon being subjected to the heat treatment cycles of essentially any electronic device manufacturing process, the wafer will form a denuded zone in the front surface layer and have a sufficient density of oxygen precipitates for IG purposes in the bulk layer.
The present invention is also directed to a wafer having a front surface, a back surface, and a central plane between the front and back surfaces, the wafer having a front surface layer consisting of the region of the wafer within a distance, D
2
, of the front surface wherein D
2
is no more than about 15 micrometers, a bulk layer comprising the region of the wafer between the central plane the front surface layer, and a denuded zone which comprises the front surface layer and a portion of the bulk layer. The wafer is characterized in that it has a substantially uniform oxygen concentration in the bulk layer, oxygen precipitates in the portion of the bulk layer which is outside the denuded zone, and a substantial absence of oxygen precipitates in the denuded zone.
The present invention is further directed to a process for heat-treating a Cz, single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, a central plane between the front and back surfaces, a vacancy sink at the front surface, a front surface layer which comprises the region of the wafer between the front surface and a distance, D
1
, measured from the front surface and toward the central plane, and a bulk layer which comprises the region of the wafer between the central plane and the distance, D
1
, measured from the front surface of the wafer. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies throughout the wafer. The concentration of vacancies in the heat-treated wafer is then reduced by controlling t
Cornara Marco
Falster Robert J.
Gambaro Daniela
Olmo Massimiliano
Kunemund Robert
MEMC Electronic Materials SpA
Senniger Powers Leavitt & Roedel
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