IDDQ testing of integrated circuits

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G06F 1100

Patent

active

057578168

ABSTRACT:
An integrated circuit includes a circuit architecture that enhances the I.sub.DDQ testability of circuitry such as random access memories. Increased accuracy and test speed are achieved by partitioning the circuit array into multiple partitions. Pairs of partitions connected to a voltage source node and having substantially identical ground line capacitances are subdivided into respective blocks. Each block in a pair of the partitions includes a corresponding block in the other partition. Each of the corresponding blocks in a pair has a substantially equal ground line capacitance, and preferably each of the blocks has a substantially equal ground line capacitance. Pairs of corresponding blocks are coupled to respective built-in current comparators. Each block is preferably configured to include portions of non-contiguous, interleaved bit line segments and portions of non-contiguous, interleaved word lines. Simultaneous test vector corresponding block write operations followed by simultaneous read operations detect a multitude of I.sub.DDQ enhancing faults such as transition faults, state coupling and bridging faults, and neighborhood pattern sensitive faults. The built-in current comparators receive I.sub.DDQ currents from respective blocks and compare the currents to a predetermined threshold current. A responsive output signal is generated to indicate a pass/fail status based upon the comparison results. Additionally, in one embodiment, test vector generation circuitry uses a single test vector modification signal to modify test vectors to improve detection of I.sub.DDQ enhancing faults.

REFERENCES:
patent: 5506499 (1996-04-01), Pupr
patent: 5592077 (1997-01-01), Runas et al.
W. K. Al-Assadi, et al.; "A Bipartite, Differential I.sub.DDQ Testable Static RAM Design;" Electrical Engineering and Computer Science Departments; Colorado State University; Fort Collins, Colorado 80523.

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