IDDQ test methodology based on the sensitivity of fault...

Details IDDQ test methodology based on the sensitivity of fault... IDDQ test methodology based on the sensitivity of fault...

2001-05-21

2003-12-16

Nguyen, Vinh P. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010

Reexamination Certificate

active

06664801

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices, and more particularly, it relates to testing of MOSFETs.
BACKGROUND OF THE INVENTION
Drain current testing of field effect transistors (FETs) is known in the art. Such drain current testing (or IDDQ testing) is performed by applying a power supply or drain-to-source voltage to a FET device. An excitation voltage is then imposed across the device from an input, such as the gate, to an output, and it is determined whether the quiescent or long-term drain-to-source current from the power source changes over time. If a defect exists, then the drain-to-source current will increase when the defect breakdown occurs.
Although such IDDQ testing can detect certain defects, other defects might not be detected in a commercially practical period of time by such testing. Thus, devices can pass IDDQ testing and can still fail in service due to defects. When failures occur in service, retrofitting or replacement of systems and components may be required. The cost of such retrofitting may greatly exceed the original price of the component.
SUMMARY OF THE INVENTION
In accordance with the present invention, an apparatus and method for performing IDDQ testing of devices are provided that overcome known problems with performing IDDQ testing of devices.
In particular, an apparatus and method for performing IDDQ testing of devices are provided that allow faults and defects to be detected that might otherwise remain in devices that pass existing IDDQ tests.
In accordance with an exemplary embodiment of the present invention, a method for testing integrated circuits is provided. The method includes providing an excitation voltage to a device, such as a MOSFET. A power supply voltage is also provided to the device, such as a drain to source voltage or VCC. The quiescent power supply current of the device is then measured, such as the IDDQ of the MOSFET. The power supply voltage to the device is then varied, and it is determined whether a change in the IDDQ of the device exceeds a predetermined allowable change.
The present invention provides many important technical advantages. One important technical advantage of the present invention is an apparatus and method for testing devices that uses changes in quiescent power supply current to detect devices with potential defects or flaws. The present invention is particularly adapted for use with IDDQ testing of MOSFET circuits, where changes in IDDQ should not occur with changes in VCC unless there is a defect or flaw in the device.
The present invention utilizes the fact that quiescent current doesn't change with VCC to address the inherent inability to choose a single go
o-go value and still account for all the IDDQ variations from lot-to-lot, wafer-to-wafer, or other sources of variation. Likewise, testing schemes that utilize multiple IDDQ measurement points with different values of VCC yield incorrect results because quiescent current does not change with VCC even for non-defective chips. This can be established by considering that IDDQ has two components: 1) parasitic diode leakage and 2) sub-threshold conduction. Parasitic diodes in the devices of an integrated circuit are either at zero-bias or reverse-biased at VCC. In either case, this component of IDDQ doesn't change with VCC. The other component of IDDQ, the sub-threshold conduction current, has been observed and proven to independent of VCC, such as by the following equation and proof:
Id =
W/L*Ido*exp[−Vbs(1
Vt) − (1/Vt)]*[1 − exp(−Vds/Vt)]*exp
[(Vgs − Vth)/(nVt)]
where
Id =
drain current
Vt =
thermal voltage (KT/q)
Vth =
threshold voltage
Vds =
drain-to-source voltage >> Vt (Vt = kT/q ~ 25 mv, Vds ~ VCC)
Vbs =
bulk-to-source voltage = 0 (bulk potential = source potential)
Vgs =
gate-to-source voltage
Ido =
constant
W =
width of MOS transistor
L =
length of MOS transistor
For the sub-threshold conduction for transistors that are turned off, every node is either at VCC or GND. Therefore, if:
Vds=0, there is no conduction at all. So, we can choose the values of
Vds=VCC and Vgs=0 for anaylsis.
As a result:
Id=~W/L*Ido*exp[(Vgs−Vth)/(nVt)]
=~W/L*Ido*exp[(−Vth)/(nVt)]
Therefore, Id is independent of VCC.


REFERENCES:
patent: 5731700 (1998-03-01), McDonald
patent: 6118293 (2000-09-01), Manhaeve et al.

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