Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-06-14
2002-06-11
Brown, Glenn W. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S073100
Reexamination Certificate
active
06404220
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an IC testing method which enables a function test and a leak current test to be performed in a brief time interval when conducting a function test and a direct current (DC) test for a semiconductor device such as a memory formed by a semiconductor integrated circuit, and to an IC testing apparatus which employs the method.
BACKGROUND ART
Heretofore, an IC testing apparatus which tests a semiconductor device such as a memory performs a function test which determines whether or not the function of the semiconductor device is normally operating and a direct current test which determines whether or not respective terminals of the semiconductor device exhibit predetermined direct current characteristics. The IC testing apparatus determines an IC which proved to be normal in both the function test and the DC test to be an acceptable product.
FIG. 3
shows a schematic arrangement of an IC testing apparatus. In this Figure, character TES designates the entire IC testing apparatus. The IC testing apparatus TES is internally categorized into a main controller MAIN, a function tester
100
and a DC tester
200
.
The main controller MAIN comprises a computer system, and controls the function tester
100
and the DC tester
200
through a bus line BUS. The function tester
100
comprises a pattern generator
102
, a timing generator
104
and function test units
106
A,
106
B, . . . ,
106
N.
The function test units
106
A-
106
N are associated with respective terminals of an IC tinder test
300
so that switches S
11
-S
1n
, can be turned on and off to have the function test units
106
A-
106
N connected with or disconnected from the respective terminals of the IC under test
300
.
Thus the function test takes place by controlling the switches S
11
-S
1n
to their on conditions to have the function test units
106
A-
106
N connected to the respective terminals of the IC under test
300
for applying test pattern signals to the respective terminals of the IC under test
300
to carry out the function test.
On the other hand, one or more DC testers
200
are provided for testing the terminals of the IC under test
300
(in the example shown in
FIG. 3
, the provision of the single DC tester
200
is shown). One or more DC testers
200
are arranged such that change-over switches S
21
-S
2n
are controlled to be on such that each DC tester
200
is connected to only one of the terminals on the IC under test
300
at a time, thus sequentially testing the DC characteristic of the specific terminals. Incidentally,
400
designates a controller which controls these switches S
11
-S
1n
and S
21
-S
2n
.
FIG. 4
shows an internal arrangement of one of the function test units,
106
A, and the summary of the function test will be described. The function test unit
106
A (the remaining function test units are similarly arranged) comprises a waveform formatter
11
, a driver
12
, a voltage comparator
13
, a logical comparator
14
and a fault analysis memory
15
.
The waveform formatter
11
receives test pattern data applied from the pattern generator
102
and produces a test pattern signal having an actual waveform. The timing generator
104
supplies a timing signal which defines the rise timing and the fall timing of the test pattern signal to the waveform formatter
11
.
The test pattern signal delivered from the waveform formatter
11
is shaped by the driver
12
into a waveform of an amplitude having a given logical value, which is fed through the switch S
11
to a given terminal on the IC under test
300
to store data in the IC under test
300
. If this terminal is an I/O terminal (a combined input and output terminal), the terminal on the IC under test
300
is set into an input mode when inputting the test pattern signal, and is switched to an output mode at the time when a write operation is performed. Content stored in the IC under test
300
is read out when switched into the output mode, and is fed through the voltage comparator
13
to the logical comparator
14
. Incidentally, when the voltage comparator
13
reads data delivered from the IC under test
300
, the output terminal of the driver
12
is set up in its high impedance mode.
The voltage comparator
13
determines by comparison whether the logic signal read out from the IC under test
300
attains a normal voltage value. Thus, voltage comparator
13
determines whether or not L logic and H logic levels are present, for example, 0.8 volt or lower and 2.4 volt or higher, respectively, and for a signal having a voltage that is a normal logic value, the appropriate logic value is input to the logical comparator
14
.
An expected value is input to the logical comparator
14
from the pattern generator
102
, and is compared against the logic value which is input from the voltage comparator
13
, thus detecting the occurrence of any non-coincidence. In the event a non-coincidence occurs, it is assumed that there exists a fault in a memory cell it an address where a write operation took place, the fault is stored in the fault analysis memory
15
at this address, and subsequent to the completion of the test, the number of faulty cells is counted by reading out the fault analysis memory
15
to determine whether or not it is possible to salvage the IC under test
300
.
FIG. 5
shows an example of the arrangement of the DC tester
200
. The arrangement shown is one which is used when the DC tester
200
operates in a voltage applied current measuring mode. A voltage V
L
or V
H
is applied to a non-inverting input terminal of an operational amplifier
16
in response to a logic value from a DA converter
17
that is applied to a terminal on the IC under test
300
.
A current detecting resistor R
1
is connected between the output terminal of the operational amplifier
16
and a current output terminal T
I
, a switch S
a2
is connected between the current output terminal T
I
and a sensing point SEN, a protective resistor R
3
is connected between the current output terminal T
I
and a voltage detecting terminal T
V
, and the voltage detecting terminal T
V
is connected to the sensing point SEN through a switch S
a1
. The sensing point SEN is connected through a change-over switch S
21
to a terminal on the IC tinder test
300
. An inverting input terminal of the operational amplifier
16
is connected to the voltage detecting terminal T
V
.
Incidentally, a switch S
b
connected in shunt with the current detecting resistor R
1
represents a range change-over switch which changes the current measuring range. By controlling the switch S
b
on, a resistor R
2
of a smaller resistance, which allows a measurement of a high current (a current in the output mode of the IC under test
300
), is connected in circuit, thus changing over to a high current measuring range.
With this arrangement of the DC tester
200
, the voltage V
L
or V
H
, applied to the non-inverting input terminal of the operational amplifier
16
from the DA converter
17
is applied to a terminal on the IC under test
300
by controlling the switches S
a1
,S
a2
and the change-over switch S
21
to on conditions.
Specifically, since the operational amplifier
16
operates to make voltages at the non-inverting and the inverting input terminal equal to each other, if V
L
, for example, is applied to the non-inverting input terminal of the operational amplifier
16
, the output voltage is controlled so that the voltage at the inverting input terminal (equal to the voltage at the voltage detecting terminal T
V
) also assumes V
L
. Accordingly, the voltage V
L
or V
H
, is applied to a terminal on the IC under test
300
.
In the DC test mode, each terminal P
i
of the IC under test
300
is set up in its input mode as shown in FIG.
6
. By measuring a current which passes through the current detecting resistor R
1
under the condition that V
1
(a voltage providing an L logic) or V
H
(a voltage providing an H logic) is applied to the terminal P
i
, respective leak currents I
Rek1
and I
Rek2
of active elements Q
1
and Q
Advantest Corporation
Brown Glenn W.
Gallagher & Lathrop
Lathrop, Esq. David N.
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