1996-09-27
1998-10-06
Decady, Albert
Excavating
327 41, G01R 3128
Patent
active
058188495
ABSTRACT:
An IC testing apparatus has a detecting circuit for detecting an inversion of an output state of a test output from an IC under test in response to application of a clock signal, a comparing circuit for comparing a value preset in a storage circuit with the output state of the test output and an output state of the detecting circuit. In a first comparison operation, the number of pulses of the clock signal applied to the IC under test is less than the number of pulses required to invert the output state of the test output by one pulse and the test output and detector output are compared with corresponding values preset in the storage circuit at times coincident with a test strobe signal synchronized with the clock signal. In a second comparison operation, another clock pulse is applied to the IC under test to make the total number of pulses equal to that needed for inverting the test output and the above comparisons are again made with corresponding preset values. A control circuit the determines whether the IC under test is good based on the comparison results.
REFERENCES:
patent: 5471484 (1995-11-01), Kawasaki
patent: 5588006 (1996-12-01), Nozuyama
patent: 5619512 (1997-04-01), Kawashima et al.
patent: 5659553 (1997-08-01), Suzuki
patent: 5663970 (1997-09-01), Bae
De'cady Albert
Iqbal Nadeem
Nippon Precision Circuits Inc.
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