1993-11-29
1996-11-26
Voeltz, Emanuel T.
Boots, shoes, and leggings
371 221, 371 251, 371 27, G06F 1100, G01R 3128
Patent
active
055792510
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to an IC tester for testing IC's such as memory IC's, logic IC's, memory IC's having a built-in logic circuit, and particularly to logic comparison for comparing an output response from an IC with an expected value.
2. Background Art
FIG. 1 illustrates a schematic diagram of a prior art IC tester in which an IC to be tested is indicated by 10.
A pattern generating section 11 comprises an algorithmic pattern generator 11A, a random pattern memory 11B, a multiplexer 11C, a control part 11D, a multiplexer 11E, and a comparison control signal generator 11F. The algorithmic pattern generator 11A generates relatively regular algorithmic pattern data AP by a logic operation in synchronism with a clock signal CK from a timing generator 12. The algorithmic pattern data AP is primarily used to generate a pattern to be applied for testing a memory, an address pattern and an expected value pattern. The random pattern memory 11B reads out a prestored random pattern RP in synchronism with the clock signal CK. The random pattern RP is primarily used to generate a pattern to be applied for testing a logic circuit and an expected value pattern. No reference will be made to the generation of the applied pattern and the address pattern, since this invention is particularly concerned with the comparison between a response output from an IC being tested and an expected value.
The multiplexer 11C is supplied with algorithmic pattern data AP from the algorithmic pattern generator 11A and a random pattern RP from the random pattern memory 11B and produces two sequences of pattern data DA and DB each having K bits by either selecting one of the data AP and RP, or combining desired portions of these data AP and RP, or taking a logical AND, a logical OR, or an exclusive-OR of the data AP and RP, in accordance with a control signal MCNT from the control part 11D. The multiplexer 11E selects and outputs the data at a desired bit position of specified one of the two sequences of the pattern data DA and DB to each of the output bit positions of the multiplexer 11E such that the outputs of N bits corresponding to N test channels CH.sub.1 -CH.sub.N are provided as desired expected value signals EXP.sub.1 -EXP.sub.N. This selection is designated by a data selecting signal DSEL and a bit selecting signal BSEL produced at a pin control interface 14. The expected value signals EXP.sub.1 -EXP.sub.N thus output from the multiplexer 11E are provided to logic comparator sections 30.sub.1 -30.sub.N of the corresponding test channels CH.sub.1 -CH.sub.N. Generating the two sequences of the pattern data DA and DB permits the use of those data to compound expected patterns having a greater number of bits than the K bits of each of the data DA and DB, for example.
Although not shown, the multiplexer 11E is equipped therein with registers each corresponding to one of the test channels. Bit selecting signals BSEL (plural bits) and data selecting signals DSEL (one bit) are set in those registers, and for each of the individual test channels, data at a specified bit position of the data DA or DB as specified by those select signals having been set are output as expected value signals.
Connected to N terminal pins of an IC 10 to be tested are level/timing comparator sections 20.sub.1 -20.sub.N of N test channels CH.sub.1 -CH.sub.N, respectively. The outputs of the level/timing comparator sections 20.sub.1 -20.sub.N are connected to logic comparator sections 30.sub.1 -30.sub.N. It is noted that the suffixes of the reference numerals 20 and 30 and the reference symbols CH and EXP represent the channel number. Each level/timing comparator section, say the comparator section 20.sub.1 and the associated logic comparator section 30.sub.1 constitute one test channel. When any one of the channels is representatively described in the following descriptions, the suffix representing the channel number may be omitted. Each level/timing comparator section 20 logically determines the
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patent: 4450560 (1984-05-01), Conner
patent: 4656632 (1987-04-01), Jackson
patent: 4860291 (1989-08-01), Damm et al.
patent: 4928278 (1990-05-01), Otsuji et al.
patent: 5142223 (1992-08-01), Higashino et al.
Advantest Corporation
Stamber Eric W.
Voeltz Emanuel T.
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