IC tester

Details IC tester IC tester

1989-08-31

1991-05-21

Jablon, Clark A.

Excavating

G06F 1122

Patent

active

050181459

ABSTRACT:
To speed up the pattern generator which is a bottleneck for speedup of an LSI tester, a continuous address control information for generating addresses for continuous pattern memory read is generated at a speed 1/N (N is an optional number larger than 1) times the operation speed of the continuous address generator, and the address controller is divided into a 1st and a 2nd address controller. The two controllers are connected via a buffer memory to ensure the normal operation when the correspondence between address control instructions and patterns to be continuously read is not 1:N. Continuous address information generated by the 1st address controller is stored in the buffer memory. The second address controller, which actually generates continuous addresses, receives the continuous address information from the buffer memory, outputs the addresses to the pattern memory at a speed N times of the operation speed of the 1st address controller, and receives the next continuous address information from the buffer memory once again when the continuous address generation is finished to repeat the operation mentioned above.

REFERENCES:
patent: 4670879 (1987-06-01), Okino
patent: 4759021 (1988-07-01), Kawaguchi
patent: 4797886 (1989-01-01), Imada
1980 IEEE Test Conference article, "100 MHz Algorithmic Pattern Generator for Memory Testing", by Masao Shimizu, et al., pp. 56-67.

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