IC test system

Details IC test system IC test system

1988-08-05

1990-05-22

Smith, Jerry

Excavating

36457101, 364579, 371 251, 371 27, 371 223, G01R 3128

Patent

active

049282786

ABSTRACT:
Calibration of timing errors of each pin electronics unit is carried out by a main controller and a plurality of controllers, each assigned to each pin electronics unit or to each block including a plurality of pin electronics units. A reference timing signal is simultaneously distributed to each pin electronics unit or block, so that the timing error calibration is executed in parallel among the pin electronics units or the blocks.

REFERENCES:
patent: 4517661 (1985-05-01), Graf et al.
patent: 4806852 (1989-02-01), Swan et al.
patent: 4827437 (1989-05-01), Blanton
Milne, B., "Timing, Not Speed, Counts the Most when Testing Fast VLSI ICs", Electronic Design, May 29, 1986, pp. 132-142.
Ichimiya et al., "Effective Test Pattern Generation for High Speed Logic LSI Testing," 1979 IEEE Test Conference, pp. 377-381.
Sugamori et al., "Analysis and Definition of Overall Timing Accuracy in VLSI Test System", 1981 IEEE Test Conference, pp. 143-153.
Skala, "Continual Autocalibration for High Timing Accuracy", 1980 IEEE Test Conference, pp. 111-116.
Deerr, "Automatic Calibration for a VLSI Test System", 1983 International Test Conference, pp. 181-187.
Grasso et al., "A 250 MHz Test System's Timing and Automatic Calibration", 1987 International Test Conference, pp. 76-84.

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