IC package with capacitors disposed on an interposal layer

Details IC package with capacitors disposed on an interposal layer IC package with capacitors disposed on an interposal layer

2011-08-02

2011-08-02

Hoang, Quoc D (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257SE23085

Reexamination Certificate

active

07989942

ABSTRACT:
An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.

REFERENCES:
patent: 6005778 (1999-12-01), Spielberger et al.
patent: 7705450 (2010-04-01), Vinson et al.
patent: 2006/0220206 (2006-10-01), Gerber et al.
patent: 2007/0085190 (2007-04-01), Vinson et al.
patent: 2007/0205505 (2007-09-01), Watanabe et al.
patent: 1020080084279 (2008-09-01), None
PCT International Search Report, Aug. 19, 2010, 3 pgs.

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