IC package encapsulating a chip under asymmetric single-side...

Details IC package encapsulating a chip under asymmetric single-side... IC package encapsulating a chip under asymmetric single-side...

2006-12-22

2008-08-05

Clark, S. V (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S686000, C257S676000

Reexamination Certificate

active

07408245

ABSTRACT:
A multi-chip IC package encapsulates a chip under asymmetric longer single-side leads. The package mainly comprises a plurality of leads that have asymmetric length at two sides of a leadframe, a plurality of die-attach tape strips, a first chip having a plurality of single-side pads under the longer side leads, at least a second chip disposed above the longer side leads, a plurality of bonding wires and a molding compound. The die-attach tape strips are mutually parallel and adhered onto the lower surfaces of the longer side leads to adhere the first chip. There is at least a mold-flow channel formed through the first chip, the longer side leads and the die-attach tape strips. The bonding wires electrically connect the single-side pads of the first chip to the leads at the two sides of the leadframe through a non-central gap. The molding compound encapsulates the first chip, the second chip, the bonding wires and portions of the leads at the two sides of the leadframe and fills up the mold-flow channel. The mold-flow channel formed by means of the die-attach tape strips may increase the encapsulated area of the first chip by the molding compound to enhance product reliability of semiconductor package.

REFERENCES:
patent: 6476474 (2002-11-01), Hung
patent: 6498391 (2002-12-01), Huang et al.
patent: 6747344 (2004-06-01), Corisis et al.
patent: 2002/0113305 (2002-08-01), Huang
patent: 2003/0214019 (2003-11-01), Chong et al.
patent: 2005/0110727 (2005-05-01), Shin
patent: 2006/0118924 (2006-06-01), Corisis et al.
patent: 2007/0246807 (2007-10-01), Hara et al.
patent: 404030 (1989-09-01), None

Affiliated with

Also associated with

Rating

IC package encapsulating a chip under asymmetric single-side... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with IC package encapsulating a chip under asymmetric single-side..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and IC package encapsulating a chip under asymmetric single-side... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3999556